yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
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* \|	Added "getting started" section to README	Clifford Wolf	2013-01-06
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* \|	Improvements in command shell	Clifford Wolf	2013-01-06
\| \| \| \| \| \| \| \| \| \| \| \|	- Added 'shell' command (run interactive shell from synth script) - Added support for ; as cmd seperator as in "proc; opt" - Fixed c++ static initialization order problem with pass register
\| *	Add support for "fsm_export" synthesis attributes to fsm_export pass.	Martin Schmölzer	2013-01-08
\|/ \| \| \| \| \| \| \| \| \| \| \| \| \|	This allows to specify the file name for exported files directly in the HDL source via the fsm_export=... attribute on the FSM state register. Verilog example: (* fsm_export="my_fsm.kiss2" *) reg [3:0] state; The fsm_export pass now also accepts the option "-noauto". This causes only FSMs with the fsm_export attribute to be exported, any other FSMs are ignored. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
*	Added a:= syntax to select framework	Clifford Wolf	2013-01-05
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*	Added qtcreator.creator.user to top level .gitignore	Clifford Wolf	2013-01-05
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*	Copy attributes from state signal to fsm cell	Clifford Wolf	2013-01-05
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*	More .gitignore and fixed "make mrproper"	Clifford Wolf	2013-01-05
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*	added more .gitignore files (make test)	Clifford Wolf	2013-01-05
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*	added .gitignore files	Clifford Wolf	2013-01-05
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*	initial import	Clifford Wolf	2013-01-05