yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed a bug in opt_const when optimizing 1-bit compares with constants	Clifford Wolf	2013-04-13
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-04-07
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\| *	Merge pull request #5 from hansiglaser/master	Clifford Wolf	2013-04-05
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\| \| *	fsm_export: optionally use binary state encoding as state names instead of	Johann Glaser	2013-04-05
\| * \|	Merge pull request #4 from hansiglaser/master	Clifford Wolf	2013-04-05
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\| \| *	fsm_export: specify KISS filename on command line	Johann Glaser	2013-04-05
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* /	Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	Clifford Wolf	2013-04-07
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*	Fixed/improved handling of colored wires in show command	Clifford Wolf	2013-04-01
*	Added support for @<set-name> in expand select ops (%x, %ci, %co)	Clifford Wolf	2013-04-01
*	Removed 4096 bytes limit for size of command from script file	Clifford Wolf	2013-04-01
*	Added -color <color> <selection> option to show command	Clifford Wolf	2013-04-01
*	Fixed "select" for "%%" stmt with emty stack	Clifford Wolf	2013-03-31
*	Added "script" command	Clifford Wolf	2013-03-31
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
*	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	Clifford Wolf	2013-03-31
*	Added k68 (m68k compatible cpu) test case from verilator	Clifford Wolf	2013-03-31
*	Improved opt_share for reduce cells	Clifford Wolf	2013-03-29
*	Improved opt_share for commutative standard cells	Clifford Wolf	2013-03-29
*	Added EXTRA_TARGETS Makefile variable	Clifford Wolf	2013-03-28
*	Improved Makefile: Added ENABLE_* switches	Clifford Wolf	2013-03-28
*	Implemented TCL support (only via -c option at the moment)	Clifford Wolf	2013-03-28
*	Improved subcircuit verbose output (added portmapper results)	Clifford Wolf	2013-03-28
*	Fixed svgviewer hacks for builtin files	Clifford Wolf	2013-03-28
*	Added proper TECHMAP_FAIL support and added support for the celltype attribut...	Clifford Wolf	2013-03-28
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
*	Keep viewport transform stable on reload in yosys-svgviewer	Clifford Wolf	2013-03-27
*	Added check: only one module for "show" unless format is "ps"	Clifford Wolf	2013-03-27
*	Now using SVG and yosys-svgviewer per default in show command	Clifford Wolf	2013-03-27
*	Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib	Clifford Wolf	2013-03-27
*	Imported svgviewer from qt4.8	Clifford Wolf	2013-03-27
*	Create nice errors when calling RTLIL::Module::derive() of base class	Clifford Wolf	2013-03-26
*	Collect parameters in hierarchy -generate (and do nothing with them)	Clifford Wolf	2013-03-26
*	Tiny bugfix in simlib.v	Clifford Wolf	2013-03-26
*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26
*	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26
*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
*	Improved verbose output of subcircuit	Clifford Wolf	2013-03-25
*	Improved method for finding fsm_expand candidates	Clifford Wolf	2013-03-25
*	Added hierarchy -generate command for generating skeletton modules	Clifford Wolf	2013-03-25
*	Changed fsm_expand to merge multiplexers more aggressively	Clifford Wolf	2013-03-24
*	Renamed hansimem.v test case to mem_arst.v	Clifford Wolf	2013-03-24
*	Fixed handling of show -viewer	Clifford Wolf	2013-03-24
*	Fixed handling of internal signals in show command	Clifford Wolf	2013-03-24
*	Improved show -colors color assignments	Clifford Wolf	2013-03-24
*	Added show -strech and renamed -widthlabels to -width	Clifford Wolf	2013-03-24
*	Added -widthlabels options to chow command	Clifford Wolf	2013-03-24
*	Added -notypes option to intersynth backend	Clifford Wolf	2013-03-24
*	Reorganized TODOs	Clifford Wolf	2013-03-24
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24