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* Implemented read_verilog -deferClifford Wolf2014-02-13
* Removed double blanks in ABC default command sequencesClifford Wolf2014-02-13
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-13
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| * Merge pull request #26 from ahmedirfan1983/btorClifford Wolf2014-02-12
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| | * modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
| | * disabling splice command in the scriptAhmed Irfan2014-02-11
| | * register output correctedAhmed Irfan2014-02-11
| | * Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-02-11
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| | * | added concat and slice cell translationAhmed Irfan2014-02-11
* | | | Updated ABC and some related changesClifford Wolf2014-02-13
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* | | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-12
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| * | | Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-12
* | | | Added support for functions returning integerClifford Wolf2014-02-12
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* | | Updated ABC to rev e97a6e1d59b9Clifford Wolf2014-02-12
* | | renamed ilang "scope error" to "ilang error"Clifford Wolf2014-02-11
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* | More Makefile cleanupsClifford Wolf2014-02-11
* | Improved "make manual" and "make clean"Clifford Wolf2014-02-11
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* Improved ilang parser error messagesClifford Wolf2014-02-09
* fixed a bug in subcircuit library with cells that have connections to itselfClifford Wolf2014-02-09
* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-09
* Added delete {-input|-output|-port}Clifford Wolf2014-02-09
* Bugfix in delete commandClifford Wolf2014-02-09
* Added test cases for expose -evert-dffClifford Wolf2014-02-08
* Fixed handling of async reset in expose -evert-dffClifford Wolf2014-02-08
* Build fixes for log cmdClifford Wolf2014-02-08
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-08
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| * Merge pull request #24 from hansiglaser/masterClifford Wolf2014-02-08
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| | * added "log" commandJohann Glaser2014-02-08
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* | Implemented expose -evert-dffClifford Wolf2014-02-08
* | Improved checking of internal cell conventionsClifford Wolf2014-02-08
* | Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collectClifford Wolf2014-02-08
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* Added various new options to splice commandClifford Wolf2014-02-08
* Added %a select operatorClifford Wolf2014-02-08
* Moved some passes to other source directoriesClifford Wolf2014-02-08
* Added support for "keep" attribute to abc passClifford Wolf2014-02-08
* Added opt -purge (frontend to opt_clean -purge)Clifford Wolf2014-02-08
* Only count non-trivial attributes when findinf master signal in opt_cleanClifford Wolf2014-02-08
* Added checking for ABC modifications to Makefile and made sure we do not have...Clifford Wolf2014-02-08
* Now also move net labes to the right position in splice cmdClifford Wolf2014-02-08
* Improved detection of primary wire for a signal in opt_cleanClifford Wolf2014-02-07
* Added splice commandClifford Wolf2014-02-07
* Added log_header() to splitnetsClifford Wolf2014-02-07
* Added $slice and $concat to CellTypes listClifford Wolf2014-02-07
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Stronger checking of internal cellsClifford Wolf2014-02-07
* Re-enabled abc "retime" after sorting yout the yosys-bigsim problemClifford Wolf2014-02-07
* Added echo commandClifford Wolf2014-02-07
* Fixed use of "cmd_error" in passes/cmds/design.ccClifford Wolf2014-02-07
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
* Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim fa...Clifford Wolf2014-02-06