yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added support for i/o buffers to iopadmap	Clifford Wolf	2013-10-26
*	Added another xilinx example (not funcional yet)	Clifford Wolf	2013-10-26
*	Added support for sr flip-flops to dfflibmap	Clifford Wolf	2013-10-24
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
*	Fixed parsing of value-less attributes in ilang	Clifford Wolf	2013-10-23
*	Improved handling of dff with async resets	Clifford Wolf	2013-10-21
*	Added handling of multiple async paths in proc_arst	Clifford Wolf	2013-10-19
*	Changed NEW_WIRE API to return the wire, not the signal	Clifford Wolf	2013-10-18
*	Added dffsr support to proc_dff pass	Clifford Wolf	2013-10-18
*	Added RTLIL NEW_WIRE macro	Clifford Wolf	2013-10-18
*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18
*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
*	Improved way of connecting ports in techmap pass	Clifford Wolf	2013-10-17
*	Only prefer connected signals iff they have public names	Clifford Wolf	2013-10-17
*	Added -buf, -true and -false options to blif backend	Clifford Wolf	2013-10-17
*	Fixed bug in synthesis of memories that are never written	Clifford Wolf	2013-10-17
*	Avoid re-arranging signals on register outputs	Clifford Wolf	2013-10-17
*	Fixed detection of major wires in opt_clean	Clifford Wolf	2013-10-17
*	Added iopadmap pass	Clifford Wolf	2013-10-16
*	Moved dfflibmap from passes/dfflibmap to passes/techmap	Clifford Wolf	2013-10-16
*	Added map, par and bitgen to xlinx7 example	Clifford Wolf	2013-10-16
*	Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'	Clifford Wolf	2013-10-16
*	Added recommended apt-get commands to README	Clifford Wolf	2013-10-11
*	Fixed minisat include	Clifford Wolf	2013-10-11
*	Pinned ABC revision to 0f9e5488ced3	Clifford Wolf	2013-10-03
*	Improvements in EDIF backend	Clifford Wolf	2013-09-17
*	Added additional options to BLIF backend	Clifford Wolf	2013-09-15
*	Added BLIF backend	Clifford Wolf	2013-09-15
*	A couple of small fixes in SPICE backend	Clifford Wolf	2013-09-15
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15
*	Updated manual	Clifford Wolf	2013-09-15
*	Added spice testbench to techlibs/cmos	Clifford Wolf	2013-09-14
*	Added spice backend	Clifford Wolf	2013-09-14
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-09-03
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\| *	Encode large (>32 bits) parameters as hex string in edif backend	Clifford Wolf	2013-08-28
\| *	Improved edif backend	Clifford Wolf	2013-08-27
\| *	Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)	Clifford Wolf	2013-08-27
* \|	Added -selected option to various backends	Clifford Wolf	2013-09-03
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*	Added simple xilinx7 technology mapping files	Clifford Wolf	2013-08-22
*	More explicit integer output in verilog backend	Clifford Wolf	2013-08-22
*	Added correct encoding of identifiers in EDIF backend	Clifford Wolf	2013-08-22
*	Added edif backend (still under construction)	Clifford Wolf	2013-08-22
*	Merge pull request #10 from hansiglaser/master	Clifford Wolf	2013-08-21
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\| *	fixed Verilog parser filename and line numbering issue with include files	Johann Glaser	2013-08-21