Commit message (Expand)AuthorAge
* Added conversion from ObjRange to std::vector and std::setClifford Wolf2014-07-27
* Added RTLIL::ObjIterator and RTLIL::ObjRangeClifford Wolf2014-07-27
* Using std::move() in SigSpec move constructorClifford Wolf2014-07-27
* Added RTLIL::SigSpec move constructor and move assignment operatorClifford Wolf2014-07-27
* Mostly cosmetic changes to rtlil.hClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* New message for completion of buildClifford Wolf2014-07-26
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added tests/various/.gitignoreClifford Wolf2014-07-26
* Added tests/various/submod_extract.ysClifford Wolf2014-07-26
* Added support for here documentsClifford Wolf2014-07-26
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Merge automatic and manual code changes for new cell connections APIClifford Wolf2014-07-26
| * Manual fixes for new cell connections APIClifford Wolf2014-07-26
| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Added some missing "const" in rtlil.hClifford Wolf2014-07-26
* Added RTLIL::Module::connections()Clifford Wolf2014-07-26
* Added RTLIL::Module::connect(const RTLIL::SigSig&)Clifford Wolf2014-07-26
* Use "wget -N" in tests/vloghtb/run-test.shClifford Wolf2014-07-26
* Added "passed" message to make test targetsClifford Wolf2014-07-26
* Automatically pack SigSpec on copy/assignClifford Wolf2014-07-26
* Added new RTLIL::Cell port access methodsClifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Cosmetic fixes for "make abc"Clifford Wolf2014-07-26
* Added "Checklist for adding internal cell types"Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
* Added RTLIL::SigSpec is_chunk()/as_chunk() APIClifford Wolf2014-07-25
* Added "make vgtest"Clifford Wolf2014-07-25
* Fixed two memory leaks in ast simplifyClifford Wolf2014-07-25
* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-25
* Fixed memory corruption in "opt_reduce" passClifford Wolf2014-07-25
* Disabled cover() for non-linux buildsClifford Wolf2014-07-25
* Added more stuff to checklistClifford Wolf2014-07-25
* Updated verific build/test instructionsClifford Wolf2014-07-25
* Improvements in "cover" commandClifford Wolf2014-07-25
* Removed Minisat dependency on zlibClifford Wolf2014-07-25
* Added more stuff to the checklistClifford Wolf2014-07-25
* Fixed typo in cover idClifford Wolf2014-07-25
* Added "make clean-abc"Clifford Wolf2014-07-25
* Further improved "make" prettinessClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Updated ABC to hg id "b1e63d18768d"Clifford Wolf2014-07-24
* Added cover() calls to opt_constClifford Wolf2014-07-24
* Added cover_list() APIClifford Wolf2014-07-24
* Added "make SMALL=1"Clifford Wolf2014-07-24