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* More Makefile cleanupsClifford Wolf2014-02-11
* Improved "make manual" and "make clean"Clifford Wolf2014-02-11
* Improved ilang parser error messagesClifford Wolf2014-02-09
* fixed a bug in subcircuit library with cells that have connections to itselfClifford Wolf2014-02-09
* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-09
* Added delete {-input|-output|-port}Clifford Wolf2014-02-09
* Bugfix in delete commandClifford Wolf2014-02-09
* Added test cases for expose -evert-dffClifford Wolf2014-02-08
* Fixed handling of async reset in expose -evert-dffClifford Wolf2014-02-08
* Build fixes for log cmdClifford Wolf2014-02-08
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-08
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| * Merge pull request #24 from hansiglaser/masterClifford Wolf2014-02-08
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| | * added "log" commandJohann Glaser2014-02-08
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* | Implemented expose -evert-dffClifford Wolf2014-02-08
* | Improved checking of internal cell conventionsClifford Wolf2014-02-08
* | Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collectClifford Wolf2014-02-08
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* Added various new options to splice commandClifford Wolf2014-02-08
* Added %a select operatorClifford Wolf2014-02-08
* Moved some passes to other source directoriesClifford Wolf2014-02-08
* Added support for "keep" attribute to abc passClifford Wolf2014-02-08
* Added opt -purge (frontend to opt_clean -purge)Clifford Wolf2014-02-08
* Only count non-trivial attributes when findinf master signal in opt_cleanClifford Wolf2014-02-08
* Added checking for ABC modifications to Makefile and made sure we do not have...Clifford Wolf2014-02-08
* Now also move net labes to the right position in splice cmdClifford Wolf2014-02-08
* Improved detection of primary wire for a signal in opt_cleanClifford Wolf2014-02-07
* Added splice commandClifford Wolf2014-02-07
* Added log_header() to splitnetsClifford Wolf2014-02-07
* Added $slice and $concat to CellTypes listClifford Wolf2014-02-07
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Stronger checking of internal cellsClifford Wolf2014-02-07
* Re-enabled abc "retime" after sorting yout the yosys-bigsim problemClifford Wolf2014-02-07
* Added echo commandClifford Wolf2014-02-07
* Fixed use of "cmd_error" in passes/cmds/design.ccClifford Wolf2014-02-07
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
* Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim fa...Clifford Wolf2014-02-06
* Updated ABC to rev 10cc13a2a0f1Clifford Wolf2014-02-06
* Added "retime" to standard ABC recipesClifford Wolf2014-02-06
* Added copy commandClifford Wolf2014-02-06
* Added design -stash/-copy-from/-copy-toClifford Wolf2014-02-06
* Added support for s: select expressions (wire width)Clifford Wolf2014-02-06
* Added i:, o:, and x: selection patternClifford Wolf2014-02-06
* Added support for %m selection opClifford Wolf2014-02-06
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-06
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| * Merge pull request #23 from hansiglaser/masterClifford Wolf2014-02-06
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| | * new %s: add sub-modules to selectionJohann Glaser2014-02-06
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* | Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-06
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* Added support for sat -show @<sel_name>Clifford Wolf2014-02-06
* Added sat -set-init-def and sat -tempinduct-defClifford Wolf2014-02-06
* Added opt_const -undrivenClifford Wolf2014-02-06
* Added expose -dffClifford Wolf2014-02-06