Commit message (Expand)AuthorAge
* Added std::initializer_list<> constructor to SigSpecClifford Wolf2014-07-28
* Added cover() to all SigSpec constructorsClifford Wolf2014-07-28
* Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-28
* Improvements in tests/vloghtbClifford Wolf2014-07-28
* Added techmap -externClifford Wolf2014-07-27
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Added topological sorting to techmapClifford Wolf2014-07-27
* Added SigPool::check(bit)Clifford Wolf2014-07-27
* Small improvements in PerformanceTimer APIClifford Wolf2014-07-27
* Fixed bug in opt_cleanClifford Wolf2014-07-27
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
* Added RTLIL::SigSpec::remove_const() handling of packed SigSpecsClifford Wolf2014-07-27
* Added RTLIL::SigSpecConstIteratorClifford Wolf2014-07-27
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
* Added log_cmd_error_expectionClifford Wolf2014-07-27
* Fixed verific bindings for new RTLIL apiClifford Wolf2014-07-27
* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-27
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
* Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-27
* Added RTLIL::Design::modules()Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Added conversion from ObjRange to std::vector and std::setClifford Wolf2014-07-27
* Added RTLIL::ObjIterator and RTLIL::ObjRangeClifford Wolf2014-07-27
* Using std::move() in SigSpec move constructorClifford Wolf2014-07-27
* Added RTLIL::SigSpec move constructor and move assignment operatorClifford Wolf2014-07-27
* Mostly cosmetic changes to rtlil.hClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* New message for completion of buildClifford Wolf2014-07-26
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added tests/various/.gitignoreClifford Wolf2014-07-26
* Added tests/various/submod_extract.ysClifford Wolf2014-07-26
* Added support for here documentsClifford Wolf2014-07-26
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Merge automatic and manual code changes for new cell connections APIClifford Wolf2014-07-26
| * Manual fixes for new cell connections APIClifford Wolf2014-07-26
| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Added some missing "const" in rtlil.hClifford Wolf2014-07-26
* Added RTLIL::Module::connections()Clifford Wolf2014-07-26
* Added RTLIL::Module::connect(const RTLIL::SigSig&)Clifford Wolf2014-07-26
* Use "wget -N" in tests/vloghtb/run-test.shClifford Wolf2014-07-26
* Added "passed" message to make test targetsClifford Wolf2014-07-26
* Automatically pack SigSpec on copy/assignClifford Wolf2014-07-26
* Added new RTLIL::Cell port access methodsClifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Cosmetic fixes for "make abc"Clifford Wolf2014-07-26
* Added "Checklist for adding internal cell types"Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26