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* Added additional options to BLIF backendClifford Wolf2013-09-15
* Added BLIF backendClifford Wolf2013-09-15
* A couple of small fixes in SPICE backendClifford Wolf2013-09-15
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Updated manualClifford Wolf2013-09-15
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
* Added spice backendClifford Wolf2013-09-14
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-09-03
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| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-28
| * Improved edif backendClifford Wolf2013-08-27
| * Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-27
* | Added -selected option to various backendsClifford Wolf2013-09-03
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* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-22
* More explicit integer output in verilog backendClifford Wolf2013-08-22
* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-22
* Added edif backend (still under construction)Clifford Wolf2013-08-22
* Merge pull request #10 from hansiglaser/masterClifford Wolf2013-08-21
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| * fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-21
* | Some minor documentation fixesClifford Wolf2013-08-21
* | Merge pull request #9 from hansiglaser/masterClifford Wolf2013-08-20
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| * Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-20
* | Merge pull request #8 from hansiglaser/masterClifford Wolf2013-08-20
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| * Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
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* Added cleaning of old version_* files to version_* make ruleClifford Wolf2013-08-20
* Added version info to yosys command and added -V optionClifford Wolf2013-08-20
* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-20
* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-15
* Fixed signed div/mod in const eval (rounding and stuff)Clifford Wolf2013-08-15
* Added ezsat api for creation of anonymous vectorsClifford Wolf2013-08-15
* Added sat -ignore_div_by_zero switchClifford Wolf2013-08-15
* Added eval -brute_force_equiv_checker_x modeClifford Wolf2013-08-15
* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
* Added SAT support for $div and $mod cellsClifford Wolf2013-08-11
* Added "clean -purge" and ";;;" supportClifford Wolf2013-08-11
* Added ";;" as shortcut for "; clean;"Clifford Wolf2013-08-11
* freduce performance fixClifford Wolf2013-08-10
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* Added techmap -opt modeClifford Wolf2013-08-09
* Some fixes to improve determinismClifford Wolf2013-08-09
* Sort ctrl signals in fsm_extractClifford Wolf2013-08-08
* Added -try option to freduce passClifford Wolf2013-08-08
* Added "clean" command (less verbose opt_clean)Clifford Wolf2013-08-08
* Fixed topological ordering in freduce passClifford Wolf2013-08-07
* Improved handling of private names in opt_clean and rename commandsClifford Wolf2013-08-07
* Added stubnets example to manual prog chapterClifford Wolf2013-08-07
* Small bugfixes in freduce passClifford Wolf2013-08-06
* Added freduce commandClifford Wolf2013-08-06