yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	updated default ABC command strings	Clifford Wolf	2014-02-13
*	Updated ABC	Clifford Wolf	2014-02-13
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
*	Removed double blanks in ABC default command sequences	Clifford Wolf	2014-02-13
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-13
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\| *	Merge pull request #26 from ahmedirfan1983/btor	Clifford Wolf	2014-02-12
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\| \| *	modified btor synthesis script for correct use of splice command.	Ahmed Irfan	2014-02-12
\| \| *	disabling splice command in the script	Ahmed Irfan	2014-02-11
\| \| *	register output corrected	Ahmed Irfan	2014-02-11
\| \| *	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	Ahmed Irfan	2014-02-11
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\| \| * \|	added concat and slice cell translation	Ahmed Irfan	2014-02-11
* \| \| \|	Updated ABC and some related changes	Clifford Wolf	2014-02-13
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* \| \|	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-12
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\| * \| \|	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	Clifford Wolf	2014-02-12
* \| \| \|	Added support for functions returning integer	Clifford Wolf	2014-02-12
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* \| \|	Updated ABC to rev e97a6e1d59b9	Clifford Wolf	2014-02-12
* \| \|	renamed ilang "scope error" to "ilang error"	Clifford Wolf	2014-02-11
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* \|	More Makefile cleanups	Clifford Wolf	2014-02-11
* \|	Improved "make manual" and "make clean"	Clifford Wolf	2014-02-11
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*	Improved ilang parser error messages	Clifford Wolf	2014-02-09
*	fixed a bug in subcircuit library with cells that have connections to itself	Clifford Wolf	2014-02-09
*	Various improvements in expose command (added -sep and -cut)	Clifford Wolf	2014-02-09
*	Added delete {-input\|-output\|-port}	Clifford Wolf	2014-02-09
*	Bugfix in delete command	Clifford Wolf	2014-02-09
*	Added test cases for expose -evert-dff	Clifford Wolf	2014-02-08
*	Fixed handling of async reset in expose -evert-dff	Clifford Wolf	2014-02-08
*	Build fixes for log cmd	Clifford Wolf	2014-02-08
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-08
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\| *	Merge pull request #24 from hansiglaser/master	Clifford Wolf	2014-02-08
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\| \| *	added "log" command	Johann Glaser	2014-02-08
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* \|	Implemented expose -evert-dff	Clifford Wolf	2014-02-08
* \|	Improved checking of internal cell conventions	Clifford Wolf	2014-02-08
* \|	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	Clifford Wolf	2014-02-08
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*	Added various new options to splice command	Clifford Wolf	2014-02-08
*	Added %a select operator	Clifford Wolf	2014-02-08
*	Moved some passes to other source directories	Clifford Wolf	2014-02-08
*	Added support for "keep" attribute to abc pass	Clifford Wolf	2014-02-08
*	Added opt -purge (frontend to opt_clean -purge)	Clifford Wolf	2014-02-08
*	Only count non-trivial attributes when findinf master signal in opt_clean	Clifford Wolf	2014-02-08
*	Added checking for ABC modifications to Makefile and made sure we do not have...	Clifford Wolf	2014-02-08
*	Now also move net labes to the right position in splice cmd	Clifford Wolf	2014-02-08
*	Improved detection of primary wire for a signal in opt_clean	Clifford Wolf	2014-02-07
*	Added splice command	Clifford Wolf	2014-02-07
*	Added log_header() to splitnets	Clifford Wolf	2014-02-07
*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
*	Stronger checking of internal cells	Clifford Wolf	2014-02-07
*	Re-enabled abc "retime" after sorting yout the yosys-bigsim problem	Clifford Wolf	2014-02-07
*	Added echo command	Clifford Wolf	2014-02-07
*	Fixed use of "cmd_error" in passes/cmds/design.cc	Clifford Wolf	2014-02-07