yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01
*	Added eval testing to test_cell	Clifford Wolf	2014-08-31
*	Fixed return size of const_*() eval functions	Clifford Wolf	2014-08-31
*	Added RTLIL::Const::size()	Clifford Wolf	2014-08-31
*	Added eval model for $lut cells	Clifford Wolf	2014-08-31
*	Typo fixes in cell->*Param() API	Clifford Wolf	2014-08-31
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31
*	Added design->scratchpad	Clifford Wolf	2014-08-30
*	Added $alu cell type	Clifford Wolf	2014-08-30
*	Added autotest -e (do not use -noexpr on write_verilog)	Clifford Wolf	2014-08-30
*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30
*	Fixed module->addPmux()	Clifford Wolf	2014-08-30
*	Using worker class in memory_map	Clifford Wolf	2014-08-30
*	Replaced $__alu CO/CS outputs with full-width CO output	Clifford Wolf	2014-08-30
*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30
*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30
*	Improved handling of $pmux cells in fsm_extract	Clifford Wolf	2014-08-30
*	Fixed inserting of Q-inverters in dfflibmap	Clifford Wolf	2014-08-27
*	Fixed printing of multi-line Makefile.conf	Clifford Wolf	2014-08-27
*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26
*	Print Makefile.conf as make info message	Clifford Wolf	2014-08-26
*	Checking for valid CONFIG value in Makefile	Clifford Wolf	2014-08-25
*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24
*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24
*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24
*	azonenberg: Make dump_vcd save model when temporal induction fails due to ste...	Clifford Wolf	2014-08-24
*	Only call proc_share_dirname() in techmap when necessary	Clifford Wolf	2014-08-23
*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
*	Added "stat -width"	Clifford Wolf	2014-08-22
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
*	Added DPI-C documentation to README file	Clifford Wolf	2014-08-22
*	Added support for non-standard <plugin>:<c_name> DPI syntax	Clifford Wolf	2014-08-22
*	Archibald Rust and Clifford Wolf: ffi-based dpi_call()	Clifford Wolf	2014-08-22
*	Added "plugin" command	Clifford Wolf	2014-08-22
*	Updated ABC to 4d547a5e065b	Clifford Wolf	2014-08-22
*	Cosmetic changes to FSM tests	Clifford Wolf	2014-08-21
*	Fixed small memory leak in ast simplify	Clifford Wolf	2014-08-21
*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21
*	Fixed memory leak in DPI function calls	Clifford Wolf	2014-08-21
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-08-21
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\| *	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19
* \|	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
* \|	Added support for global tasks and functions	Clifford Wolf	2014-08-21
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*	Using "via_celltype" in $mul carry-save-acc implementation	Clifford Wolf	2014-08-18
*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
*	Performance fix for new $__lcu techmap rule	Clifford Wolf	2014-08-18
*	Replaced recursive lcu scheme with bk adder	Clifford Wolf	2014-08-18