summaryrefslogtreecommitdiff
Commit message (Expand)AuthorAge
...
* Improved handling of relational op of real valuesClifford Wolf2014-06-17
* Little steps in realmath test benchClifford Wolf2014-06-16
* Improved ternary support for real valuesClifford Wolf2014-06-16
* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-16
* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-16
* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
* Added more calls to "hierarchy" to README fileClifford Wolf2014-06-15
* Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...Clifford Wolf2014-06-15
* Added tests/realmath to "make test"Clifford Wolf2014-06-15
* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-15
* Improved realmath test benchClifford Wolf2014-06-15
* Improved parsing of large integer constantsClifford Wolf2014-06-15
* Improved AstNode::asReal for large integersClifford Wolf2014-06-15
* improved realmath test benchClifford Wolf2014-06-14
* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
* progress in realmath test benchClifford Wolf2014-06-14
* Fixed relational operators for const real expressionsClifford Wolf2014-06-14
* added first draft of real math testcase generatorClifford Wolf2014-06-14
* Progress in presentationClifford Wolf2014-06-14
* Added %D and %c select commandsClifford Wolf2014-06-14
* Added support for math functionsClifford Wolf2014-06-14
* Added realexpr.v test caseClifford Wolf2014-06-14
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
* Implemented more real arithmeticClifford Wolf2014-06-14
* Implemented basic real arithmeticClifford Wolf2014-06-14
* Added real->int convertion in ast genrtlilClifford Wolf2014-06-14
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* Now we are in Yoys 0.3.0+ developmentClifford Wolf2014-06-08
* Tagging Yosys 0.3.0Clifford Wolf2014-06-08
* Updated ABC to 7600ffb9340cClifford Wolf2014-06-08
* added tests for new verilog featuresClifford Wolf2014-06-07
* fixed cell array handling of positional argumentsClifford Wolf2014-06-07
* Add support for cell arraysClifford Wolf2014-06-07
* Added support for repeat stmt in const functionsClifford Wolf2014-06-07
* further improved const function supportClifford Wolf2014-06-07
* made the generate..endgenrate keywords optionalClifford Wolf2014-06-06
* improved const function supportClifford Wolf2014-06-06
* fix functions with no block (but single statement, loop, etc.)Clifford Wolf2014-06-06
* Added tests/simple/repwhile.vClifford Wolf2014-06-06
* improved ast simplify of const functionsClifford Wolf2014-06-06
* added while and repeat support to verilog parserClifford Wolf2014-06-06
* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-04
* added tee cmdClifford Wolf2014-06-03
* Fixed log messages in memory_dffClifford Wolf2014-06-01
* Updated ABC to rev fa4404b395f0Clifford Wolf2014-05-29
* Merge pull request #36 from hansiglaser/masterClifford Wolf2014-05-29
|\
| * added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-28
| * new flags -ignore_miss_func and -ignore_miss_dir for read_libertyJohann Glaser2014-05-28
| * be more verbose when techmap yielded processesJohann Glaser2014-05-26
|/