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* Improved handling of relational op of real valuesClifford Wolf2014-06-17
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* Little steps in realmath test benchClifford Wolf2014-06-16
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* Improved ternary support for real valuesClifford Wolf2014-06-16
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* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-16
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* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-16
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* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
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* Added more calls to "hierarchy" to README fileClifford Wolf2014-06-15
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* Removed long running tests from tests/simple/realexpr.v (replaced by ↵Clifford Wolf2014-06-15
| | | | tests/realmath)
* Added tests/realmath to "make test"Clifford Wolf2014-06-15
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* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-15
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* Improved realmath test benchClifford Wolf2014-06-15
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* Improved parsing of large integer constantsClifford Wolf2014-06-15
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* Improved AstNode::asReal for large integersClifford Wolf2014-06-15
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* improved realmath test benchClifford Wolf2014-06-14
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* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
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* progress in realmath test benchClifford Wolf2014-06-14
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* Fixed relational operators for const real expressionsClifford Wolf2014-06-14
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* added first draft of real math testcase generatorClifford Wolf2014-06-14
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* Progress in presentationClifford Wolf2014-06-14
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* Added %D and %c select commandsClifford Wolf2014-06-14
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* Added support for math functionsClifford Wolf2014-06-14
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* Added realexpr.v test caseClifford Wolf2014-06-14
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* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
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* Implemented more real arithmeticClifford Wolf2014-06-14
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* Implemented basic real arithmeticClifford Wolf2014-06-14
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* Added real->int convertion in ast genrtlilClifford Wolf2014-06-14
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* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
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* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
| | | | allways_ff, always_comb, and always_latch
* Now we are in Yoys 0.3.0+ developmentClifford Wolf2014-06-08
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* Tagging Yosys 0.3.0Clifford Wolf2014-06-08
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* Updated ABC to 7600ffb9340cClifford Wolf2014-06-08
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* added tests for new verilog featuresClifford Wolf2014-06-07
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* fixed cell array handling of positional argumentsClifford Wolf2014-06-07
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* Add support for cell arraysClifford Wolf2014-06-07
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* Added support for repeat stmt in const functionsClifford Wolf2014-06-07
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* further improved const function supportClifford Wolf2014-06-07
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* made the generate..endgenrate keywords optionalClifford Wolf2014-06-06
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* improved const function supportClifford Wolf2014-06-06
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* fix functions with no block (but single statement, loop, etc.)Clifford Wolf2014-06-06
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* Added tests/simple/repwhile.vClifford Wolf2014-06-06
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* improved ast simplify of const functionsClifford Wolf2014-06-06
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* added while and repeat support to verilog parserClifford Wolf2014-06-06
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* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-04
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* added tee cmdClifford Wolf2014-06-03
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* Fixed log messages in memory_dffClifford Wolf2014-06-01
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* Updated ABC to rev fa4404b395f0Clifford Wolf2014-05-29
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* Merge pull request #36 from hansiglaser/masterClifford Wolf2014-05-29
|\ | | | | Various changes merged
| * added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-28
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| * new flags -ignore_miss_func and -ignore_miss_dir for read_libertyJohann Glaser2014-05-28
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| * be more verbose when techmap yielded processesJohann Glaser2014-05-26
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