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Fixed handling of [a-fxz?] in decimal constants
Clifford Wolf
2015-08-11
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Added missing ct_all setup to opt_clean
Clifford Wolf
2015-08-11
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Use MEMID as name for $mem cell
Clifford Wolf
2015-08-09
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Merge pull request #69 from zeldin/master
Clifford Wolf
2015-08-07
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Added iCE40 WARMBOOT cell
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Added iCE40 WARMBOOT cell
Marcus Comstedt
2015-08-06
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Remove some very strange whitespace in btor.cc (by Larry Doolittle)
Clifford Wolf
2015-08-05
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Bugfix in SMV back-end for partially unassigned wires
Clifford Wolf
2015-08-05
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Added ENABLE_LIBYOSYS Makefile option
Clifford Wolf
2015-08-04
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Added $assert support to SMV back-end
Clifford Wolf
2015-08-04
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Added libyosys.so build
Clifford Wolf
2015-08-04
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Merge pull request #68 from zeldin/master
Clifford Wolf
2015-08-01
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Add -noautowire option to verilog frontend
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Add -noautowire option to verilog frontend
Marcus Comstedt
2015-08-01
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Added WORDS parameter to $meminit
Clifford Wolf
2015-07-31
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Fixed flatten $meminit handling
Clifford Wolf
2015-07-30
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Improvements in BLIF back-end
Clifford Wolf
2015-07-29
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Fixed nested mem2reg
Clifford Wolf
2015-07-29
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Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
Clifford Wolf
2015-07-27
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Fixed "check" command for inout ports
Clifford Wolf
2015-07-27
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Some cleanups in opt_rmdff
Clifford Wolf
2015-07-25
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Added "miter -assert"
Clifford Wolf
2015-07-25
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Keep modules with $assume (like $assert)
Clifford Wolf
2015-07-25
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Improved $adff simplification
Clifford Wolf
2015-07-24
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iCE40 DFF sim models: init Q regs to 0
Clifford Wolf
2015-07-20
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Fixed techmap processes error msg
Clifford Wolf
2015-07-18
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Avoid tristate warning for blackbox ice40/cells_sim.v
Clifford Wolf
2015-07-18
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Some fixes in "select" command
Clifford Wolf
2015-07-16
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Fixed YosysJS.create_worker() usage of this.url_prefix
Clifford Wolf
2015-07-10
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Improved liberty file test case
Clifford Wolf
2015-07-06
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Updated ABC
Clifford Wolf
2015-07-06
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Do not collect disabled $memwr cells
Clifford Wolf
2015-07-06
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Improved YosysJS WebWorker API
Clifford Wolf
2015-07-04
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Bugfix in fsm_extract
Clifford Wolf
2015-07-03
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Added "synth -nofsm"
Clifford Wolf
2015-07-02
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Added opt_const -clkinv
Clifford Wolf
2015-07-01
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Added logic-loop error handling to freduce
Clifford Wolf
2015-06-30
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2015-06-30
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Added YosysJS.create_worker()
Clifford Wolf
2015-06-28
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Bugfix in chparam
Clifford Wolf
2015-06-30
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Added design->rename(module, new_name)
Clifford Wolf
2015-06-30
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iCE40: set min bram efficiency to 2%
Clifford Wolf
2015-06-20
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Using static mem size of 128 MB in emcc build
Clifford Wolf
2015-06-20
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Added init support to SMV back-end
Clifford Wolf
2015-06-19
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Progress in SMV back-end
Clifford Wolf
2015-06-19
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Progress in SMV back-end
Clifford Wolf
2015-06-19
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Progress in SMV back-end
Clifford Wolf
2015-06-18
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Progress in SMV back-end
Clifford Wolf
2015-06-17
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Added "rename -top new_name"
Clifford Wolf
2015-06-17
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Progress in SMV back-end
Clifford Wolf
2015-06-17
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Progress in SMV back-end
Clifford Wolf
2015-06-16
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