yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12
*	Improved handling of "keep" attributes in hierarchical designs in opt_clean	Clifford Wolf	2015-08-12
*	Fixed hashlib for 64 bit int keys	Clifford Wolf	2015-08-12
*	Added SMV back-end 'test_cells.sh' script	Clifford Wolf	2015-08-12
*	Merge pull request #70 from gaomy3832/bugfix	Clifford Wolf	2015-08-12
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\| *	Remove unused blackbox modules in opt_clean.	Mingyu Gao	2015-08-11
\| *	Bugfix for cell hash cache option in opt_share.	Mingyu Gao	2015-08-10
* \|	Bugfix for cell hash cache option in opt_share.	Mingyu Gao	2015-08-11
* \|	Fixed handling of [a-fxz?] in decimal constants	Clifford Wolf	2015-08-11
* \|	Added missing ct_all setup to opt_clean	Clifford Wolf	2015-08-11
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*	Use MEMID as name for $mem cell	Clifford Wolf	2015-08-09
*	Merge pull request #69 from zeldin/master	Clifford Wolf	2015-08-07
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\| *	Added iCE40 WARMBOOT cell	Marcus Comstedt	2015-08-06
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*	Remove some very strange whitespace in btor.cc (by Larry Doolittle)	Clifford Wolf	2015-08-05
*	Bugfix in SMV back-end for partially unassigned wires	Clifford Wolf	2015-08-05
*	Added ENABLE_LIBYOSYS Makefile option	Clifford Wolf	2015-08-04
*	Added $assert support to SMV back-end	Clifford Wolf	2015-08-04
*	Added libyosys.so build	Clifford Wolf	2015-08-04
*	Merge pull request #68 from zeldin/master	Clifford Wolf	2015-08-01
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\| *	Add -noautowire option to verilog frontend	Marcus Comstedt	2015-08-01
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*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31
*	Fixed flatten $meminit handling	Clifford Wolf	2015-07-30
*	Improvements in BLIF back-end	Clifford Wolf	2015-07-29
*	Fixed nested mem2reg	Clifford Wolf	2015-07-29
*	Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)	Clifford Wolf	2015-07-27
*	Fixed "check" command for inout ports	Clifford Wolf	2015-07-27
*	Some cleanups in opt_rmdff	Clifford Wolf	2015-07-25
*	Added "miter -assert"	Clifford Wolf	2015-07-25
*	Keep modules with $assume (like $assert)	Clifford Wolf	2015-07-25
*	Improved $adff simplification	Clifford Wolf	2015-07-24
*	iCE40 DFF sim models: init Q regs to 0	Clifford Wolf	2015-07-20
*	Fixed techmap processes error msg	Clifford Wolf	2015-07-18
*	Avoid tristate warning for blackbox ice40/cells_sim.v	Clifford Wolf	2015-07-18
*	Some fixes in "select" command	Clifford Wolf	2015-07-16
*	Fixed YosysJS.create_worker() usage of this.url_prefix	Clifford Wolf	2015-07-10
*	Improved liberty file test case	Clifford Wolf	2015-07-06
*	Updated ABC	Clifford Wolf	2015-07-06
*	Do not collect disabled $memwr cells	Clifford Wolf	2015-07-06
*	Improved YosysJS WebWorker API	Clifford Wolf	2015-07-04
*	Bugfix in fsm_extract	Clifford Wolf	2015-07-03
*	Added "synth -nofsm"	Clifford Wolf	2015-07-02
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Added opt_const -clkinv	Clifford Wolf	2015-07-01
*	Added logic-loop error handling to freduce	Clifford Wolf	2015-06-30
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-06-30
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\| *	Added YosysJS.create_worker()	Clifford Wolf	2015-06-28
* \|	Bugfix in chparam	Clifford Wolf	2015-06-30
* \|	Added design->rename(module, new_name)	Clifford Wolf	2015-06-30
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*	iCE40: set min bram efficiency to 2%	Clifford Wolf	2015-06-20
*	Using static mem size of 128 MB in emcc build	Clifford Wolf	2015-06-20