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* Added logic-loop error handling to freduceClifford Wolf2015-06-30
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-06-30
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| * Added YosysJS.create_worker()Clifford Wolf2015-06-28
* | Bugfix in chparamClifford Wolf2015-06-30
* | Added design->rename(module, new_name)Clifford Wolf2015-06-30
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* iCE40: set min bram efficiency to 2%Clifford Wolf2015-06-20
* Using static mem size of 128 MB in emcc buildClifford Wolf2015-06-20
* Added init support to SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-18
* Progress in SMV back-endClifford Wolf2015-06-17
* Added "rename -top new_name"Clifford Wolf2015-06-17
* Progress in SMV back-endClifford Wolf2015-06-17
* Progress in SMV back-endClifford Wolf2015-06-16
* Added "synth -nordff -noalumacc"Clifford Wolf2015-06-15
* Progress in SMV back-endClifford Wolf2015-06-15
* Progress in SMV back-endClifford Wolf2015-06-15
* Added "write_smv" skeletonClifford Wolf2015-06-15
* Removed debug code from write_smt2Clifford Wolf2015-06-14
* Modernized memory_dff (and fixed a bug)Clifford Wolf2015-06-14
* Added "memory -nordff"Clifford Wolf2015-06-14
* Added write_smt2 -memClifford Wolf2015-06-14
* Makefile fix for YosysJS buildClifford Wolf2015-06-11
* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-11
* Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-11
* AigMaker refactoringClifford Wolf2015-06-10
* Added "json -aig"Clifford Wolf2015-06-10
* Renamed "aig" to "aigmap"Clifford Wolf2015-06-10
* Fixed cellaigs port extendingClifford Wolf2015-06-10
* Added "aig" passClifford Wolf2015-06-09
* synth_ice40 now flattens by defaultClifford Wolf2015-06-09
* Added cellaigs APIClifford Wolf2015-06-09
* Merge clock inverters in memory_dffClifford Wolf2015-06-09
* Merge branch 'verilog-backend-memV2' of github.com:wluker/yosysClifford Wolf2015-06-09
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| * $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-08
| * Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-04
* | Fixed "avail_parameters" handling in module clone/copyClifford Wolf2015-06-08
* | Added log_dump() support for IdStringsClifford Wolf2015-06-08
* | Fixed handling of parameters with reversed rangeClifford Wolf2015-06-08
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* Added opt_share -share_allClifford Wolf2015-05-31
* Added iCE40 PLL cellsClifford Wolf2015-05-31
* Added liberty dont_use support to dfflibmapClifford Wolf2015-05-31
* Fixed signedness of genvar expressionsClifford Wolf2015-05-29
* Added output args to synth_ice40Clifford Wolf2015-05-26
* Improvements in BLIF front-endClifford Wolf2015-05-24
* improved ice40 SB_IO sim modelClifford Wolf2015-05-23
* Improved "flatten" handlings of inout portsClifford Wolf2015-05-23
* Added simple $dlatch support to opt_rmdffClifford Wolf2015-05-23
* Added ice40 SB_IO sim modelClifford Wolf2015-05-23
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