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* Fixed vhdl2verilog temp dir nameClifford Wolf2014-03-01
* Fixed vhdl2verilog help messageClifford Wolf2014-03-01
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
* Fixed bit-extending in $mux argument (use $bu0 instead of $pos)Clifford Wolf2014-02-26
* Added support for $bu0 to SatGenClifford Wolf2014-02-26
* Don't blow up constants unneccessarily in Verilog frontendClifford Wolf2014-02-24
* Added support for Minisat::SimpSolver + ezSAT frezze() APIClifford Wolf2014-02-23
* Fixed small memory leak in Pass::call()Clifford Wolf2014-02-23
* Fixed bug in generation of undefs for $memwr MUXesClifford Wolf2014-02-22
* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-22
* Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-22
* Added ezMiniSat EZMINISAT_INCREMENTAL compile-time optionClifford Wolf2014-02-22
* Made MiniSat solver backend configurable in ezminisat.hClifford Wolf2014-02-22
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
* Added vhdl2verilogClifford Wolf2014-02-21
* Progress in presentationClifford Wolf2014-02-21
* Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-21
* Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-21
* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-21
* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-21
* Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-21
* Progress in presentationClifford Wolf2014-02-21
* Progress in presentationClifford Wolf2014-02-20
* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-20
* Added "extract -map %<design_name>"Clifford Wolf2014-02-20
* Added "design -push" and "design -pop"Clifford Wolf2014-02-20
* Progress in presentationClifford Wolf2014-02-20
* Added connwrappers commandClifford Wolf2014-02-20
* Cleanups in handling of read_verilog -defer and -icellsClifford Wolf2014-02-20
* Progress in presentationClifford Wolf2014-02-20
* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-19
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-18
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| * Added "sat -dump_cnf"Clifford Wolf2014-02-18
| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
| * Improved non-verbose ezSAT::printDIMACS() formatClifford Wolf2014-02-18
| * Added "sat -initsteps"Clifford Wolf2014-02-18
* | Progress in presentationClifford Wolf2014-02-18
* | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-18
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* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-17
* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-17
* Progress in presentationClifford Wolf2014-02-17
* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-17
* Progress in presentationClifford Wolf2014-02-16
* Added some additional checks to techmapClifford Wolf2014-02-16
* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-16
* Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-16
* Added a warning note about error reporting to read_verilog help messageClifford Wolf2014-02-16
* Progress in presentationClifford Wolf2014-02-16