yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Fixed vhdl2verilog temp dir name	Clifford Wolf	2014-03-01
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*	Fixed vhdl2verilog help message	Clifford Wolf	2014-03-01
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*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27
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*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26
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*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26
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*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24
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*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23
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*	Fixed small memory leak in Pass::call()	Clifford Wolf	2014-02-23
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*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22
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*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22
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*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22
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*	Added ezMiniSat EZMINISAT_INCREMENTAL compile-time option	Clifford Wolf	2014-02-22
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*	Made MiniSat solver backend configurable in ezminisat.h	Clifford Wolf	2014-02-22
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*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21
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*	Added vhdl2verilog	Clifford Wolf	2014-02-21
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*	Progress in presentation	Clifford Wolf	2014-02-21
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*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21
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*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21
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*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21
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*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21
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*	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21
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*	Progress in presentation	Clifford Wolf	2014-02-21
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*	Progress in presentation	Clifford Wolf	2014-02-20
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*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20
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*	Added "extract -ignore_parameters" and "extract -ignore_param ..."	Clifford Wolf	2014-02-20
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*	Added "extract -map %<design_name>"	Clifford Wolf	2014-02-20
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*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20
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*	Progress in presentation	Clifford Wolf	2014-02-20
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*	Added connwrappers command	Clifford Wolf	2014-02-20
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*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20
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*	Progress in presentation	Clifford Wolf	2014-02-20
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*	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	Clifford Wolf	2014-02-19
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-18
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\| *	Added "sat -dump_cnf"	Clifford Wolf	2014-02-18
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\| *	Coding style corrections in SatHelper::dump_model_to_vcd()	Clifford Wolf	2014-02-18
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\| *	Improved non-verbose ezSAT::printDIMACS() format	Clifford Wolf	2014-02-18
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\| *	Added "sat -initsteps"	Clifford Wolf	2014-02-18
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* \|	Progress in presentation	Clifford Wolf	2014-02-18
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* \|	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
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*	Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups	Clifford Wolf	2014-02-17
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*	Added "-dump_fail_to_vcd" argument to SAT solver	Andrew Zonenberg	2014-02-17
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*	Progress in presentation	Clifford Wolf	2014-02-17
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*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17
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*	Progress in presentation	Clifford Wolf	2014-02-16
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*	Added some additional checks to techmap	Clifford Wolf	2014-02-16
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*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16
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*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16
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*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16
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*	Progress in presentation	Clifford Wolf	2014-02-16
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