summaryrefslogtreecommitdiff
Commit message (Expand)AuthorAge
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Removed old doc references to $safe_pmuxClifford Wolf2014-08-15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-15
* document "techmap -map %<design-name>"Clifford Wolf2014-08-15
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-15
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
* Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-14
* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-14
* Fixed handling of task outputsClifford Wolf2014-08-14
* Simplified $__arraymul techmap ruleClifford Wolf2014-08-14
* Added module->portsClifford Wolf2014-08-14
* Refactoring of CellType classClifford Wolf2014-08-14
* RIP $safe_pmuxClifford Wolf2014-08-14
* Some improvements in FSM mapping and recodingClifford Wolf2014-08-14
* Added "abc -D" for setting delay targetClifford Wolf2014-08-14
* Updated ABC to 4935c2b946deClifford Wolf2014-08-14
* Added techmap support for actual lookahead carry unitClifford Wolf2014-08-13
* Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-13
* Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-13
* New interface for $__alu in techmap.vClifford Wolf2014-08-13
* Added support for non-standard """ macro bodiesClifford Wolf2014-08-13
* Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-12
* Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-12
* Fixed SigBit(RTLIL::Wire *wire) constructorClifford Wolf2014-08-12
* Fixed building verific bindingsClifford Wolf2014-08-12
* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-12
* Another build fix by americanrouter (via reddit)Clifford Wolf2014-08-11
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-10
* Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-09
* Do not share any $reduce_* cells (its complicated and not worth it anyways)Clifford Wolf2014-08-09
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-09
* Improved FSM testsClifford Wolf2014-08-08
* Another fsm_extract bugfixClifford Wolf2014-08-08
* Fixed "fsm -export"Clifford Wolf2014-08-08
* Fixed sharing of reduce operatorClifford Wolf2014-08-08
* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-08
* Added FSM test benchClifford Wolf2014-08-08
* Added "sat -prove-skip"Clifford Wolf2014-08-08
* Fixed build with gcc-4.6Clifford Wolf2014-08-07
* Use "-keepdc" in "miter -equiv -flatten"Clifford Wolf2014-08-07
* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-07
* Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-07
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
* Various improvements in memory_dff passClifford Wolf2014-08-06
* Various fixes and improvements in wreduce passClifford Wolf2014-08-05
* Removed old "constmap" from wreduce codeClifford Wolf2014-08-05
* Added support for truncating of wires to wreduce passClifford Wolf2014-08-05
* Cleanups and improvements in wreduce passClifford Wolf2014-08-05