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*
Added mux support to wreduce command
Clifford Wolf
2014-08-05
*
Improved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf
2014-08-05
*
Fixed AST handling of variables declared inside a functions main block
Clifford Wolf
2014-08-05
*
Added "show -signed"
Clifford Wolf
2014-08-04
*
Added support for non-standard "module mod_name(...);" syntax
Clifford Wolf
2014-08-04
*
Added RTLIL::IdString::in(...)
Clifford Wolf
2014-08-04
*
Fixed "share" for memory read ports
Clifford Wolf
2014-08-03
*
Added "wreduce" to some of the standard test benches
Clifford Wolf
2014-08-03
*
Progress in "wreduce" pass
Clifford Wolf
2014-08-03
*
Added "wreduce" command (work in progress)
Clifford Wolf
2014-08-03
*
Added query() API to ModIndex
Clifford Wolf
2014-08-03
*
Added ID() macro for static IdStrings
Clifford Wolf
2014-08-03
*
Implemented recursive techmap
Clifford Wolf
2014-08-03
*
Fixes in show command (related to new IdString)
Clifford Wolf
2014-08-03
*
Implemented simplemap support for "techmap -extern"
Clifford Wolf
2014-08-02
*
Fixed a va_list corruption in logv_error()
Clifford Wolf
2014-08-02
*
Be more conservative with printing decimal numbers in verilog backend
Clifford Wolf
2014-08-02
*
Improved verilog output for ordinary $mux cells
Clifford Wolf
2014-08-02
*
Bugfix in "techmap -extern"
Clifford Wolf
2014-08-02
*
Removed at() method from RTLIL::IdString
Clifford Wolf
2014-08-02
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
*
Limit size of log_signal buffer to 100 elements
Clifford Wolf
2014-08-02
*
Improvements in new RTLIL::IdString implementation
Clifford Wolf
2014-08-02
*
Fixed a performance bug in opt_reduce
Clifford Wolf
2014-08-02
*
Implemented new reference counting RTLIL::IdString
Clifford Wolf
2014-08-02
*
Fixed memory corruption related to id2cstr()
Clifford Wolf
2014-08-02
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
*
Added logfile hash to statistics footer
Clifford Wolf
2014-08-01
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
*
Added per-pass cpu usage statistics
Clifford Wolf
2014-08-01
*
Added ModIndex helper class, some changes to RTLIL::Monitor
Clifford Wolf
2014-08-01
*
Packed SigBit::data and SigBit::offset in a union
Clifford Wolf
2014-08-01
*
Consolidated hana test benches into fewer files
Clifford Wolf
2014-08-01
*
Added "test_autotb -n <num_iter>" option
Clifford Wolf
2014-08-01
*
Renamed modwalker.h to modtools.h
Clifford Wolf
2014-07-31
*
Various cleanups in Makefile, Renamed default configurations
Clifford Wolf
2014-07-31
*
Added compiler + compiler version + compiler flags to version string
Clifford Wolf
2014-07-31
*
Fixed build of verific bindings
Clifford Wolf
2014-07-31
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added "trace" command
Clifford Wolf
2014-07-31
*
Added RTLIL::Monitor
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
*
Added "techmap -assert"
Clifford Wolf
2014-07-31
*
Reorganized stdcells.v (no actual code change, just moved and indented stuff)
Clifford Wolf
2014-07-31
*
Added "yosys -A"
Clifford Wolf
2014-07-31
*
Added "yosys -Q"
Clifford Wolf
2014-07-31
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