yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
*	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	Clifford Wolf	2013-03-31
*	Added k68 (m68k compatible cpu) test case from verilator	Clifford Wolf	2013-03-31
*	Improved opt_share for reduce cells	Clifford Wolf	2013-03-29
*	Improved opt_share for commutative standard cells	Clifford Wolf	2013-03-29
*	Added EXTRA_TARGETS Makefile variable	Clifford Wolf	2013-03-28
*	Improved Makefile: Added ENABLE_* switches	Clifford Wolf	2013-03-28
*	Implemented TCL support (only via -c option at the moment)	Clifford Wolf	2013-03-28
*	Improved subcircuit verbose output (added portmapper results)	Clifford Wolf	2013-03-28
*	Fixed svgviewer hacks for builtin files	Clifford Wolf	2013-03-28
*	Added proper TECHMAP_FAIL support and added support for the celltype attribut...	Clifford Wolf	2013-03-28
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
*	Keep viewport transform stable on reload in yosys-svgviewer	Clifford Wolf	2013-03-27
*	Added check: only one module for "show" unless format is "ps"	Clifford Wolf	2013-03-27
*	Now using SVG and yosys-svgviewer per default in show command	Clifford Wolf	2013-03-27
*	Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib	Clifford Wolf	2013-03-27
*	Imported svgviewer from qt4.8	Clifford Wolf	2013-03-27
*	Create nice errors when calling RTLIL::Module::derive() of base class	Clifford Wolf	2013-03-26
*	Collect parameters in hierarchy -generate (and do nothing with them)	Clifford Wolf	2013-03-26
*	Tiny bugfix in simlib.v	Clifford Wolf	2013-03-26
*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26
*	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26
*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
*	Improved verbose output of subcircuit	Clifford Wolf	2013-03-25
*	Improved method for finding fsm_expand candidates	Clifford Wolf	2013-03-25
*	Added hierarchy -generate command for generating skeletton modules	Clifford Wolf	2013-03-25
*	Changed fsm_expand to merge multiplexers more aggressively	Clifford Wolf	2013-03-24
*	Renamed hansimem.v test case to mem_arst.v	Clifford Wolf	2013-03-24
*	Fixed handling of show -viewer	Clifford Wolf	2013-03-24
*	Fixed handling of internal signals in show command	Clifford Wolf	2013-03-24
*	Improved show -colors color assignments	Clifford Wolf	2013-03-24
*	Added show -strech and renamed -widthlabels to -width	Clifford Wolf	2013-03-24
*	Added -widthlabels options to chow command	Clifford Wolf	2013-03-24
*	Added -notypes option to intersynth backend	Clifford Wolf	2013-03-24
*	Reorganized TODOs	Clifford Wolf	2013-03-24
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24
*	Fixed stdcells.v for $adff with undef reset value	Clifford Wolf	2013-03-24
*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24
*	Added -colors option to show command	Clifford Wolf	2013-03-24
*	Added hansimem testcase (memory with async reset)	Clifford Wolf	2013-03-24
*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24
*	Fixed gcc build (intersynth backend)	Clifford Wolf	2013-03-23
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23
*	Various improvements in intersynth backend	Clifford Wolf	2013-03-23
*	Added intersynth backend	Clifford Wolf	2013-03-23
*	Added help -write-tex-command-reference-manual option	Clifford Wolf	2013-03-21
*	Added eclipse CDT project files to .gitignore	Clifford Wolf	2013-03-21
*	Added -S option for simple synthesis to gate logic	Clifford Wolf	2013-03-21
*	Avoid verilog-2k in verilog backend	Clifford Wolf	2013-03-21