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* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* Some fixes in libs/minisat (thanks to Siesh1oo)Clifford Wolf2014-03-12
* - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-12
* Fixed dependencies of "make test"Clifford Wolf2014-03-12
* Added libs/minisat (copy of minisat git master)Clifford Wolf2014-03-12
* OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/...Clifford Wolf2014-03-11
* Merged addition of SED makefile variable from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Added support for `line compiler directiveClifford Wolf2014-03-11
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-11
* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-11
* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-11
* Fixed a typo in RTLIL::Module::addReduce...Clifford Wolf2014-03-10
* Improved verific command (added support for some operators)Clifford Wolf2014-03-10
* Improvements in verific commandClifford Wolf2014-03-10
* Added RTLIL::Module::add... helper methodsClifford Wolf2014-03-10
* Added "verific" commandClifford Wolf2014-03-09
* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-09
* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-09
* Fixed bug in freduce commandClifford Wolf2014-03-07
* Some minor code cleanups in freduce commandClifford Wolf2014-03-07
* Bugfix in ilang frontend autoidx recoveryClifford Wolf2014-03-07
* Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-07
* Added freduce -dumpClifford Wolf2014-03-06
* Added freduce -stopClifford Wolf2014-03-06
* Fixed gcc compiler warningClifford Wolf2014-03-06
* Fixed undef handling in opt_reduceClifford Wolf2014-03-06
* Fixes for improved techmap of shifts with large B inputsClifford Wolf2014-03-06
* Fixed use of frozen literals in SatGenClifford Wolf2014-03-06
* Strictly zero-extend unsigned A-inputs of shift operations in techmapClifford Wolf2014-03-06
* Added techmap -max_iter optionClifford Wolf2014-03-06
* Improved techmap of shift with wide B inputsClifford Wolf2014-03-06
* Strictly zero-extend unsigned A-inputs of shift operationsClifford Wolf2014-03-06
* Switched to EZMINISAT_SIMPSOLVER as default SAT solverClifford Wolf2014-03-05
* Include id2ast pointers when dumping ASTClifford Wolf2014-03-05
* Fixed merging of compatible wire decls in AST frontendClifford Wolf2014-03-05
* Bugfix in recursive AST simplificationClifford Wolf2014-03-05
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-03
* ezSAT: Added frozen_literal() APIClifford Wolf2014-03-03
* ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressionsClifford Wolf2014-03-03
* Added ezSAT::eliminated API to help the SAT solver remember eliminated variablesClifford Wolf2014-03-01
* ezSAT bugfix: don't call virtual methods in base class constructorClifford Wolf2014-03-01
* Removed ezSAT::assumed() APIClifford Wolf2014-03-01
* Removed ezSAT built-in brute-froce solverClifford Wolf2014-03-01
* Fixed vhdl2verilog temp dir nameClifford Wolf2014-03-01
* Fixed vhdl2verilog help messageClifford Wolf2014-03-01
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
* Fixed bit-extending in $mux argument (use $bu0 instead of $pos)Clifford Wolf2014-02-26
* Added support for $bu0 to SatGenClifford Wolf2014-02-26
* Don't blow up constants unneccessarily in Verilog frontendClifford Wolf2014-02-24