Commit message (Expand)AuthorAge
* Improved (added -d option)Clifford Wolf2013-05-14
* Some improvements in vcdcd.plClifford Wolf2013-05-14
* Added support for verilog === operatorClifford Wolf2013-05-07
* Added tcl "yosys -import" commandClifford Wolf2013-05-02
* Improved/simplified TCL bindingsClifford Wolf2013-05-01
* Added support for const cell inputs in techmapClifford Wolf2013-04-27
* Fixed README for new show command behavior (svg vs. ps)Clifford Wolf2013-04-27
* Added "flatten" passClifford Wolf2013-04-26
* Fixed handling of positional module parametersClifford Wolf2013-04-26
* Fixed hierarchy pass for hierarchies of parametric modulesClifford Wolf2013-04-26
* Only use sha1 checksums for names of parametric modules when the verbose form...Clifford Wolf2013-04-26
* Fixed "show -format ..." command line parsingClifford Wolf2013-04-15
* Added "submod -name ..." supportClifford Wolf2013-04-15
* Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-13
* Fixed a bug in opt_const when optimizing 1-bit compares with constantsClifford Wolf2013-04-13
* Merge branch 'master' of Wolf2013-04-07
| * Merge pull request #5 from hansiglaser/masterClifford Wolf2013-04-05
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| | * fsm_export: optionally use binary state encoding as state names instead ofJohann Glaser2013-04-05
| * | Merge pull request #4 from hansiglaser/masterClifford Wolf2013-04-05
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| | * fsm_export: specify KISS filename on command lineJohann Glaser2013-04-05
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* | Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-07
* Fixed/improved handling of colored wires in show commandClifford Wolf2013-04-01
* Added support for @<set-name> in expand select ops (%x, %ci, %co)Clifford Wolf2013-04-01
* Removed 4096 bytes limit for size of command from script fileClifford Wolf2013-04-01
* Added -color <color> <selection> option to show commandClifford Wolf2013-04-01
* Fixed "select" for "%%" stmt with emty stackClifford Wolf2013-03-31
* Added "script" commandClifford Wolf2013-03-31
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-31
* Added k68 (m68k compatible cpu) test case from verilatorClifford Wolf2013-03-31
* Improved opt_share for reduce cellsClifford Wolf2013-03-29
* Improved opt_share for commutative standard cellsClifford Wolf2013-03-29
* Added EXTRA_TARGETS Makefile variableClifford Wolf2013-03-28
* Improved Makefile: Added ENABLE_* switchesClifford Wolf2013-03-28
* Implemented TCL support (only via -c option at the moment)Clifford Wolf2013-03-28
* Improved subcircuit verbose output (added portmapper results)Clifford Wolf2013-03-28
* Fixed svgviewer hacks for builtin filesClifford Wolf2013-03-28
* Added proper TECHMAP_FAIL support and added support for the celltype attribut...Clifford Wolf2013-03-28
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Keep viewport transform stable on reload in yosys-svgviewerClifford Wolf2013-03-27
* Added check: only one module for "show" unless format is "ps"Clifford Wolf2013-03-27
* Now using SVG and yosys-svgviewer per default in show commandClifford Wolf2013-03-27
* Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlibClifford Wolf2013-03-27
* Imported svgviewer from qt4.8Clifford Wolf2013-03-27
* Create nice errors when calling RTLIL::Module::derive() of base classClifford Wolf2013-03-26
* Collect parameters in hierarchy -generate (and do nothing with them)Clifford Wolf2013-03-26
* Tiny bugfix in simlib.vClifford Wolf2013-03-26
* Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
* Fixed handling of unconditional generate blocksClifford Wolf2013-03-26