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Debian dgit repo for package yosys
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Author
Age
*
Improved attributes API and handling of "src" attributes
Clifford Wolf
2015-04-24
*
Added support for initialized xilinx brams
Clifford Wolf
2015-04-06
*
Added "keep_hierarchy" attribute
Clifford Wolf
2015-02-25
*
Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf
2015-02-14
*
Auto-detect TCL version
Clifford Wolf
2015-02-05
*
Added onehot attribute
Clifford Wolf
2015-02-04
*
Minor README changes
Clifford Wolf
2015-02-01
*
Removed TODO list from README file
Clifford Wolf
2015-02-01
*
Added yosys_banner(), Updated Copyright range
Clifford Wolf
2015-02-01
*
README stuff
Clifford Wolf
2015-01-20
*
Removed psmisc from deps list (usually fuser is already installed and the pac...
Clifford Wolf
2014-12-14
*
Added psmisc to prerequisites
Clifford Wolf
2014-12-12
*
Added missing prerequisites to README
Clifford Wolf
2014-12-12
*
Improved nomem2reg documentation
Clifford Wolf
2014-10-30
*
Added support for $readmemh/$readmemb
Clifford Wolf
2014-10-26
*
Added support for "keep" on modules
Clifford Wolf
2014-09-29
*
Added "synth" command
Clifford Wolf
2014-09-14
*
Removed yosys-svgviewer
Clifford Wolf
2014-09-02
*
Using "xdot" instead of "yosys-svgviewer" in show command
Clifford Wolf
2014-09-02
*
Added DPI-C documentation to README file
Clifford Wolf
2014-08-22
*
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
Clifford Wolf
2014-08-22
*
Added "via_celltype" attribute on task/func
Clifford Wolf
2014-08-18
*
Added support for non-standard """ macro bodies
Clifford Wolf
2014-08-13
*
Added AST_MULTIRANGE (arrays with more than 1 dimension)
Clifford Wolf
2014-08-06
*
Added support for non-standard "module mod_name(...);" syntax
Clifford Wolf
2014-08-04
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
*
Added links to some liberty files to README
Clifford Wolf
2014-06-28
*
Added more calls to "hierarchy" to README file
Clifford Wolf
2014-06-15
*
Added read_verilog -sv options, added support for bit, logic,
Clifford Wolf
2014-06-12
*
Updated README
Clifford Wolf
2014-04-18
*
Added libs/minisat (copy of minisat git master)
Clifford Wolf
2014-03-12
*
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
*
Updated todo items in README file
Clifford Wolf
2014-02-05
*
Added constant size expression support of sized constants
Clifford Wolf
2014-02-01
*
Added note about SystemVerilog assert statement to README
Clifford Wolf
2014-02-01
*
Tiny change in example script in README
Clifford Wolf
2014-01-29
*
Fixes and other changes in README
Clifford Wolf
2013-12-08
*
Tighter integration of ABC build
Clifford Wolf
2013-11-27
*
Updated TODOs
Clifford Wolf
2013-11-24
*
Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Enable {* .. *} feature per default (removes dependency to REJECT feature in ...
Clifford Wolf
2013-11-22
*
Implemented indexed part selects
Clifford Wolf
2013-11-20
*
Fixed name resolution of local tasks and functions in generate block
Clifford Wolf
2013-11-20
*
Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
*
Updated TODOs in README file
Clifford Wolf
2013-11-20
*
Added init= attribute for fpga-style reset values
Clifford Wolf
2013-11-20
*
Removed done or obsolete TODO items
Clifford Wolf
2013-11-07
*
Added support for "keep" attributes on wires
Clifford Wolf
2013-11-05
*
Added roadmap to readme file
Clifford Wolf
2013-11-02
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