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* Removed yosys-svgviewerClifford Wolf2014-09-02
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-02
* Added DPI-C documentation to README fileClifford Wolf2014-08-22
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-22
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-18
* Added support for non-standard """ macro bodiesClifford Wolf2014-08-13
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-04
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Added links to some liberty files to READMEClifford Wolf2014-06-28
* Added more calls to "hierarchy" to README fileClifford Wolf2014-06-15
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* Updated READMEClifford Wolf2014-04-18
* Added libs/minisat (copy of minisat git master)Clifford Wolf2014-03-12
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Updated todo items in README fileClifford Wolf2014-02-05
* Added constant size expression support of sized constantsClifford Wolf2014-02-01
* Added note about SystemVerilog assert statement to READMEClifford Wolf2014-02-01
* Tiny change in example script in READMEClifford Wolf2014-01-29
* Fixes and other changes in READMEClifford Wolf2013-12-08
* Tighter integration of ABC buildClifford Wolf2013-11-27
* Updated TODOsClifford Wolf2013-11-24
* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Implemented indexed part selectsClifford Wolf2013-11-20
* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-20
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Updated TODOs in README fileClifford Wolf2013-11-20
* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-20
* Removed done or obsolete TODO itemsClifford Wolf2013-11-07
* Added support for "keep" attributes on wiresClifford Wolf2013-11-05
* Added roadmap to readme fileClifford Wolf2013-11-02
* Added paragraph to README file to avoid mycells.lib confusionClifford Wolf2013-10-31
* README file typo fixClifford Wolf2013-10-31
* Some additions to the README fileClifford Wolf2013-10-31
* Added iopadmap passClifford Wolf2013-10-16
* Added recommended apt-get commands to READMEClifford Wolf2013-10-11
* Updated TODO section in READMEClifford Wolf2013-08-01
* Added web site link to READMEClifford Wolf2013-07-21
* Added ast frontend refactoring to TODOClifford Wolf2013-07-11
* Documentation updatesClifford Wolf2013-07-04
* Added "make abc" and "make install-abc"Clifford Wolf2013-06-08
* Fixed README for new show command behavior (svg vs. ps)Clifford Wolf2013-04-27
* Implemented TCL support (only via -c option at the moment)Clifford Wolf2013-03-28
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* Reorganized TODOsClifford Wolf2013-03-24
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* added a TODOJohann Glaser2013-03-18