yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added "synth" command	Clifford Wolf	2014-09-14
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*	Removed yosys-svgviewer	Clifford Wolf	2014-09-02
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*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02
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*	Added DPI-C documentation to README file	Clifford Wolf	2014-08-22
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*	Archibald Rust and Clifford Wolf: ffi-based dpi_call()	Clifford Wolf	2014-08-22
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*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
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*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
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*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
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*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
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*	Added links to some liberty files to README	Clifford Wolf	2014-06-28
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*	Added more calls to "hierarchy" to README file	Clifford Wolf	2014-06-15
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*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12
\| \| \| \|	allways_ff, always_comb, and always_latch
*	Updated README	Clifford Wolf	2014-04-18
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*	Added libs/minisat (copy of minisat git master)	Clifford Wolf	2014-03-12
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*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Updated todo items in README file	Clifford Wolf	2014-02-05
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
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*	Added note about SystemVerilog assert statement to README	Clifford Wolf	2014-02-01
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*	Tiny change in example script in README	Clifford Wolf	2014-01-29
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*	Fixes and other changes in README	Clifford Wolf	2013-12-08
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*	Tighter integration of ABC build	Clifford Wolf	2013-11-27
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*	Updated TODOs	Clifford Wolf	2013-11-24
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵	Clifford Wolf	2013-11-22
\| \| \| \|	flex)
*	Implemented indexed part selects	Clifford Wolf	2013-11-20
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*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
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*	Updated TODOs in README file	Clifford Wolf	2013-11-20
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*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20
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*	Removed done or obsolete TODO items	Clifford Wolf	2013-11-07
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*	Added support for "keep" attributes on wires	Clifford Wolf	2013-11-05
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*	Added roadmap to readme file	Clifford Wolf	2013-11-02
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*	Added paragraph to README file to avoid mycells.lib confusion	Clifford Wolf	2013-10-31
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*	README file typo fix	Clifford Wolf	2013-10-31
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*	Some additions to the README file	Clifford Wolf	2013-10-31
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*	Added iopadmap pass	Clifford Wolf	2013-10-16
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*	Added recommended apt-get commands to README	Clifford Wolf	2013-10-11
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*	Updated TODO section in README	Clifford Wolf	2013-08-01
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*	Added web site link to README	Clifford Wolf	2013-07-21
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*	Added ast frontend refactoring to TODO	Clifford Wolf	2013-07-11
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*	Documentation updates	Clifford Wolf	2013-07-04
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*	Added "make abc" and "make install-abc"	Clifford Wolf	2013-06-08
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*	Fixed README for new show command behavior (svg vs. ps)	Clifford Wolf	2013-04-27
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*	Implemented TCL support (only via -c option at the moment)	Clifford Wolf	2013-03-28
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
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*	Reorganized TODOs	Clifford Wolf	2013-03-24
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*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24
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