path: root/backends/btor/
Commit message (Expand)AuthorAge
* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Squashed commit of the following:Ruben Undheim2016-09-23
* Added "int ceil_log2(int)" functionClifford Wolf2016-02-13
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Remove some very strange whitespace in (by Larry Doolittle)Clifford Wolf2015-08-05
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-11
* separated memory next from write cellAhmed Irfan2015-04-03
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-24
* namespace YosysClifford Wolf2014-09-27
* Merge branch 'master' of into btorAhmed Irfan2014-09-22
| * Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
| * Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
| * No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
| * More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
| * Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
| * Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
| * Using log_assert() instead of assert()Clifford Wolf2014-07-28
| * Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
| * Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
| * Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
| * More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
| * Manual fixes for new cell connections APIClifford Wolf2014-07-26
| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| * Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
| * Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
| * SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
| * SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
| * Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-07
* | fixed memory next issue, when same memory is written in different case statementahmedirfan19832014-09-18
* | added $pmux cell translationAhmed Irfan2014-09-02
* register output correctedAhmed Irfan2014-02-11
* added concat and slice cell translationAhmed Irfan2014-02-11
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
* Added BTOR backend README fileClifford Wolf2014-02-05
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* root bug correctedAhmed Irfan2014-01-25
* removed regex includeAhmed Irfan2014-01-24
* merged clifford changes + removed regexAhmed Irfan2014-01-24
* slice bug correctedAhmed Irfan2014-01-20
* assert featureAhmed Irfan2014-01-20
* verilog default options pullAhmed Irfan2014-01-17
* slice error correctedAhmed Irfan2014-01-16
* width issuesAhmed Irfan2014-01-15
* BTOR backendAhmed Irfan2014-01-14
* btorAhmed Irfan2014-01-03