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path: root/backends/btor/verilog2btor.sh
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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-22
| | | | | | | | | added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
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* disabling splice command in the scriptAhmed Irfan2014-02-11
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* added concat and slice cell translationAhmed Irfan2014-02-11
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
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* Use techmap -share_map in btor scriptsClifford Wolf2014-01-24
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* Moved btor scripts to backends/btor/Clifford Wolf2014-01-24