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* namespace YosysClifford Wolf2014-09-27
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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-22
|\ | | | | | | | | | | | | | | | | added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
| * Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-01
| | | | | | | | RTLIL::SigChunk::data
| * Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
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| * No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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| * More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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| * Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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| * Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
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| * Using log_assert() instead of assert()Clifford Wolf2014-07-28
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| * Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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| * Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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| * Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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| * More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
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| * Manual fixes for new cell connections APIClifford Wolf2014-07-26
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| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
| * Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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| * Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
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| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | | | | | created interim RTLIL::SigSpec::chunks_rw()
| * SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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| * SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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| * Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-07
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* | fixed memory next issue, when same memory is written in different case statementahmedirfan19832014-09-18
| | | | | | | | fixed reduce_xnor, logic_not bug translation bug
* | added $pmux cell translationAhmed Irfan2014-09-02
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* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
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* disabling splice command in the scriptAhmed Irfan2014-02-11
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* register output correctedAhmed Irfan2014-02-11
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* added concat and slice cell translationAhmed Irfan2014-02-11
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* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
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* Added BTOR backend README fileClifford Wolf2014-02-05
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
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* root bug correctedAhmed Irfan2014-01-25
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* removed regex includeAhmed Irfan2014-01-24
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* merged clifford changes + removed regexAhmed Irfan2014-01-24
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* Use techmap -share_map in btor scriptsClifford Wolf2014-01-24
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* Moved btor scripts to backends/btor/Clifford Wolf2014-01-24
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* slice bug correctedAhmed Irfan2014-01-20
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* assert featureAhmed Irfan2014-01-20
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* verilog default options pullAhmed Irfan2014-01-17
| | | | shift operator width issues
* slice error correctedAhmed Irfan2014-01-16
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* width issuesAhmed Irfan2014-01-15
| | | | dff cell for more than one registers
* BTOR backendAhmed Irfan2014-01-14
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* btorAhmed Irfan2014-01-03
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