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* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-07
* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
* disabling splice command in the scriptAhmed Irfan2014-02-11
* register output correctedAhmed Irfan2014-02-11
* added concat and slice cell translationAhmed Irfan2014-02-11
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
* Added BTOR backend README fileClifford Wolf2014-02-05
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* root bug correctedAhmed Irfan2014-01-25
* removed regex includeAhmed Irfan2014-01-24
* merged clifford changes + removed regexAhmed Irfan2014-01-24
* Use techmap -share_map in btor scriptsClifford Wolf2014-01-24
* Moved btor scripts to backends/btor/Clifford Wolf2014-01-24
* slice bug correctedAhmed Irfan2014-01-20
* assert featureAhmed Irfan2014-01-20
* verilog default options pullAhmed Irfan2014-01-17
* slice error correctedAhmed Irfan2014-01-16
* width issuesAhmed Irfan2014-01-15
* BTOR backendAhmed Irfan2014-01-14
* btorAhmed Irfan2014-01-03