yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Use log_abort() and log_assert() in BTOR backend	Clifford Wolf	2014-03-07
*	modified btor synthesis script for correct use of splice command.	Ahmed Irfan	2014-02-12
*	disabling splice command in the script	Ahmed Irfan	2014-02-11
*	register output corrected	Ahmed Irfan	2014-02-11
*	added concat and slice cell translation	Ahmed Irfan	2014-02-11
*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06
*	Added BTOR backend README file	Clifford Wolf	2014-02-05
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	root bug corrected	Ahmed Irfan	2014-01-25
*	removed regex include	Ahmed Irfan	2014-01-24
*	merged clifford changes + removed regex	Ahmed Irfan	2014-01-24
*	Use techmap -share_map in btor scripts	Clifford Wolf	2014-01-24
*	Moved btor scripts to backends/btor/	Clifford Wolf	2014-01-24
*	slice bug corrected	Ahmed Irfan	2014-01-20
*	assert feature	Ahmed Irfan	2014-01-20
*	verilog default options pull	Ahmed Irfan	2014-01-17
*	slice error corrected	Ahmed Irfan	2014-01-16
*	width issues	Ahmed Irfan	2014-01-15
*	BTOR backend	Ahmed Irfan	2014-01-14
*	btor	Ahmed Irfan	2014-01-03