yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	New upstream version 0.9	Ruben Undheim	2019-10-18
*	Imported GIT HEAD: 0.8+20190328git32bd0f2	Ruben Undheim	2019-03-28
*	New upstream version 0.8	Ruben Undheim	2018-10-17
*	New upstream version 0.7+20181007git9850de4	Ruben Undheim	2018-10-15
*	New upstream version 0.7+20180830git0b7a184	Ruben Undheim	2018-08-30
*	Squashed commit of the following:	Ruben Undheim	2016-09-23
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Added EDIF backend support for multi-bit cell ports	Clifford Wolf	2015-02-01
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Improved comments on topological sort in edif backend	Clifford Wolf	2013-11-04
*	Added simple topological sort to edif backend	Clifford Wolf	2013-11-03
*	Write yosys version to output files	Clifford Wolf	2013-11-03
*	Fixed hex string generation bug in edif backend	Clifford Wolf	2013-10-27
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24
*	Improvements in EDIF backend	Clifford Wolf	2013-09-17
*	Encode large (>32 bits) parameters as hex string in edif backend	Clifford Wolf	2013-08-28
*	Improved edif backend	Clifford Wolf	2013-08-27
*	Added correct encoding of identifiers in EDIF backend	Clifford Wolf	2013-08-22
*	Added edif backend (still under construction)	Clifford Wolf	2013-08-22