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* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* Added support for dump -appendClifford Wolf2014-02-04
* Updated manual/command-reference-manual.texClifford Wolf2013-12-28
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added dump -m and -n optionsClifford Wolf2013-11-29
* Added support for signed parameters in ilangClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Write yosys version to output filesClifford Wolf2013-11-03
* Added -selected option to various backendsClifford Wolf2013-09-03
* Fixed generation of newlines in "dump" outputClifford Wolf2013-06-10
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-02
* Added more help messagesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05