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* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
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* Silenced a gcc warning in spice backendClifford Wolf2013-11-09
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* Write yosys version to output filesClifford Wolf2013-11-03
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* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
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* A couple of small fixes in SPICE backendClifford Wolf2013-09-15
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* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
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* Added spice backendClifford Wolf2013-09-14