Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 |
* | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 |
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
* | Added "top" attribute to mark top module in hierarchy | Clifford Wolf | 2013-11-24 |
* | Renamed "placeholder" to "blackbox" | Clifford Wolf | 2013-11-22 |
* | Silenced a gcc warning in spice backend | Clifford Wolf | 2013-11-09 |
* | Write yosys version to output files | Clifford Wolf | 2013-11-03 |
* | Fixed handling of boolean attributes (backends) | Clifford Wolf | 2013-10-24 |
* | A couple of small fixes in SPICE backend | Clifford Wolf | 2013-09-15 |
* | Added spice testbench to techlibs/cmos | Clifford Wolf | 2013-09-14 |
* | Added spice backend | Clifford Wolf | 2013-09-14 |