path: root/backends/verilog
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* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20181007git9850de4Ruben Undheim2018-10-15
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Bugfixes in writing of memories as VerilogClifford Wolf2015-09-25
* Another block of spelling fixesLarry Doolittle2015-08-14
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-14
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Fixed trailing whitespacesClifford Wolf2015-07-02
* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-08
* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-04
* Some fixes for $mem in verilog back-endClifford Wolf2015-05-20
* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-11
| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-11
* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-10
* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-10
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-08
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-07
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-09
* Added "init" attribute support to verilog backendClifford Wolf2015-04-04
* Added Verilog backend $dffsr supportClifford Wolf2015-03-18
* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-13
* Added dict/pool.sort()Clifford Wolf2015-01-24
* Cosmetic changes in verilog output formatClifford Wolf2015-01-02
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-26
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Added $dffe support to write_verilogClifford Wolf2014-12-20
* Fixed generation of temp names in verilog backendClifford Wolf2014-11-07
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Using $pos models for $bu0Clifford Wolf2014-09-03
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Refactoring of CellType classClifford Wolf2014-08-14
* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26