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verilog
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verilog_backend.cc
Commit message (
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Author
Age
*
Imported yosys 0.7
Ruben Undheim
2016-11-03
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Squashed commit of the following:
Ruben Undheim
2016-09-23
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Bugfixes in writing of memories as Verilog
Clifford Wolf
2015-09-25
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Another block of spelling fixes
Larry Doolittle
2015-08-14
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Re-created command-reference-manual.tex, copied some doc fixes to online help
Clifford Wolf
2015-08-14
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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$mem cell in verilog backend : grouped writes by clock
luke whittlesey
2015-06-08
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Bug fix in $mem verilog backend + changed tests/bram flow of make test.
luke whittlesey
2015-06-04
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Some fixes for $mem in verilog back-end
Clifford Wolf
2015-05-20
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Merge pull request #63 from wluker/verilog-backend-mem
Clifford Wolf
2015-05-11
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Fixed bug in $mem cell verilog code generation.
luke whittlesey
2015-05-11
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Disabled broken $mem support in verilog backend
Clifford Wolf
2015-05-10
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Made changes recommended by Clifford Wolf ...
luke whittlesey
2015-05-10
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Verilog backend for $mem cells should now be able to handle different
luke whittlesey
2015-05-08
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Added support for $mem cells in the verilog backend.
luke whittlesey
2015-05-07
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Minor fixes in handling of "init" attribute
Clifford Wolf
2015-04-09
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Added "init" attribute support to verilog backend
Clifford Wolf
2015-04-04
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Added Verilog backend $dffsr support
Clifford Wolf
2015-03-18
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Fixed "write_verilog -attr2comment" handling of "*/" in strings
Clifford Wolf
2015-02-13
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Added dict/pool.sort()
Clifford Wolf
2015-01-24
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Cosmetic changes in verilog output format
Clifford Wolf
2015-01-02
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Replaced std::unordered_map as implementation for Yosys::dict
Clifford Wolf
2014-12-26
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Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
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Added $dffe support to write_verilog
Clifford Wolf
2014-12-20
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Fixed generation of temp names in verilog backend
Clifford Wolf
2014-11-07
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Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
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namespace Yosys
Clifford Wolf
2014-09-27
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Various bug fixes (related to $macc model testing)
Clifford Wolf
2014-09-06
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Removed $bu0 cell type
Clifford Wolf
2014-09-04
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Using $pos models for $bu0
Clifford Wolf
2014-09-03
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Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
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Fixed AOI/OAI expr handling in verilog backend
Clifford Wolf
2014-08-16
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
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Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
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Refactoring of CellType class
Clifford Wolf
2014-08-14
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Be more conservative with printing decimal numbers in verilog backend
Clifford Wolf
2014-08-02
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Improved verilog output for ordinary $mux cells
Clifford Wolf
2014-08-02
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More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
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Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
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Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
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Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
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Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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Various RTLIL::SigSpec related code cleanups
Clifford Wolf
2014-07-25
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