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path: root/backends/verilog/verilog_backend.cc
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* Added dict/pool.sort()Clifford Wolf2015-01-24
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* Cosmetic changes in verilog output formatClifford Wolf2015-01-02
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* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-26
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
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* Added $dffe support to write_verilogClifford Wolf2014-12-20
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* Fixed generation of temp names in verilog backendClifford Wolf2014-11-07
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
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* namespace YosysClifford Wolf2014-09-27
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* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
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* Removed $bu0 cell typeClifford Wolf2014-09-04
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* Using $pos models for $bu0Clifford Wolf2014-09-03
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* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
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* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-16
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-16
| | | | $_OAI4_
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
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* Refactoring of CellType classClifford Wolf2014-08-14
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* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
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* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog ↵Clifford Wolf2014-07-20
| | | | backend
* Added support for $bu0 to verilog backendClifford Wolf2014-07-20
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* Added $slice and $concat cell typesClifford Wolf2014-02-07
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
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* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-24
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
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* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
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* Write yosys version to output filesClifford Wolf2013-11-03
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* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
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* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
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* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
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* Added -selected option to various backendsClifford Wolf2013-09-03
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* More explicit integer output in verilog backendClifford Wolf2013-08-22
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