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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...Clifford Wolf2014-07-20
* Added support for $bu0 to verilog backendClifford Wolf2014-07-20
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
* Write yosys version to output filesClifford Wolf2013-11-03
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Added -selected option to various backendsClifford Wolf2013-09-03
* More explicit integer output in verilog backendClifford Wolf2013-08-22
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Avoid verilog-2k in verilog backendClifford Wolf2013-03-21
* More support code for $sr cellsClifford Wolf2013-03-14
* Fixed a gcc compiler warning [-Wparentheses]Clifford Wolf2013-03-03
* Added more help messagesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05