yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
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*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21
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*	Write yosys version to output files	Clifford Wolf	2013-11-03
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*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24
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*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
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*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
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*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
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*	Added -selected option to various backends	Clifford Wolf	2013-09-03
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*	More explicit integer output in verilog backend	Clifford Wolf	2013-08-22
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
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*	Avoid verilog-2k in verilog backend	Clifford Wolf	2013-03-21
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*	More support code for $sr cells	Clifford Wolf	2013-03-14
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*	Fixed a gcc compiler warning [-Wparentheses]	Clifford Wolf	2013-03-03
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*	Added more help messages	Clifford Wolf	2013-03-01
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*	initial import	Clifford Wolf	2013-01-05