path: root/backends/verilog
Commit message (Expand)AuthorAge
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Added -selected option to various backendsClifford Wolf2013-09-03
* More explicit integer output in verilog backendClifford Wolf2013-08-22
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Avoid verilog-2k in verilog backendClifford Wolf2013-03-21
* More support code for $sr cellsClifford Wolf2013-03-14
* Fixed a gcc compiler warning [-Wparentheses]Clifford Wolf2013-03-03
* Added more help messagesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05