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* Minor fixes in handling of "init" attributeClifford Wolf2015-04-09
* Added "init" attribute support to verilog backendClifford Wolf2015-04-04
* Added Verilog backend $dffsr supportClifford Wolf2015-03-18
* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-13
* Added dict/pool.sort()Clifford Wolf2015-01-24
* Cosmetic changes in verilog output formatClifford Wolf2015-01-02
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-26
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Added $dffe support to write_verilogClifford Wolf2014-12-20
* Fixed generation of temp names in verilog backendClifford Wolf2014-11-07
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Using $pos models for $bu0Clifford Wolf2014-09-03
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Refactoring of CellType classClifford Wolf2014-08-14
* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...Clifford Wolf2014-07-20
* Added support for $bu0 to verilog backendClifford Wolf2014-07-20
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
* Write yosys version to output filesClifford Wolf2013-11-03
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24