yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Cosmetic changes in verilog output format	Clifford Wolf	2015-01-02
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Added $dffe support to write_verilog	Clifford Wolf	2014-12-20
*	Fixed generation of temp names in verilog backend	Clifford Wolf	2014-11-07
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Using $pos models for $bu0	Clifford Wolf	2014-09-03
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
*	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	Refactoring of CellType class	Clifford Wolf	2014-08-14
*	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02
*	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...	Clifford Wolf	2014-07-20
*	Added support for $bu0 to verilog backend	Clifford Wolf	2014-07-20
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21
*	Write yosys version to output files	Clifford Wolf	2013-11-03
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
*	Added -selected option to various backends	Clifford Wolf	2013-09-03
*	More explicit integer output in verilog backend	Clifford Wolf	2013-08-22
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28