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*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Added "int ceil_log2(int)" function
Clifford Wolf
2016-02-13
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Added "write_blif -cname" mode
Clifford Wolf
2016-01-06
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Added yosys-smtbmc -S
Clifford Wolf
2015-12-20
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Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
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renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Clifford Wolf
2015-10-24
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Progress in yosys-smtbmc
Clifford Wolf
2015-10-15
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Improvements in yosys-smtbmc
Clifford Wolf
2015-10-15
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More "yosys-smtbmc -c" fixes
Clifford Wolf
2015-10-14
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Fixed yosys-smtbmc -c
Clifford Wolf
2015-10-14
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Added yosys-smtbmc copyright
Clifford Wolf
2015-10-14
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Improvements in yosys-smtbmc
Clifford Wolf
2015-10-14
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Added yosys-smtbmc
Clifford Wolf
2015-10-14
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Implemented smtbmc.py -i
Clifford Wolf
2015-10-14
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Added smtbmc.py
Clifford Wolf
2015-10-13
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Added write_smt2 -wires
Clifford Wolf
2015-10-13
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Bugfixes in writing of memories as Verilog
Clifford Wolf
2015-09-25
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Added "yosys-smt2-wire" tag support to smt2 back-end
Clifford Wolf
2015-08-31
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Fixed generation of smt2 concat statements
Clifford Wolf
2015-08-15
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Another block of spelling fixes
Larry Doolittle
2015-08-14
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Re-created command-reference-manual.tex, copied some doc fixes to online help
Clifford Wolf
2015-08-14
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
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Added "write_smt2 -regs"
Clifford Wolf
2015-08-12
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Added SMV back-end 'test_cells.sh' script
Clifford Wolf
2015-08-12
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Use MEMID as name for $mem cell
Clifford Wolf
2015-08-09
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Remove some very strange whitespace in btor.cc (by Larry Doolittle)
Clifford Wolf
2015-08-05
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Bugfix in SMV back-end for partially unassigned wires
Clifford Wolf
2015-08-05
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Added $assert support to SMV back-end
Clifford Wolf
2015-08-04
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Improvements in BLIF back-end
Clifford Wolf
2015-07-29
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Added init support to SMV back-end
Clifford Wolf
2015-06-19
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Progress in SMV back-end
Clifford Wolf
2015-06-19
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Progress in SMV back-end
Clifford Wolf
2015-06-19
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Progress in SMV back-end
Clifford Wolf
2015-06-18
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Progress in SMV back-end
Clifford Wolf
2015-06-17
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Progress in SMV back-end
Clifford Wolf
2015-06-17
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Progress in SMV back-end
Clifford Wolf
2015-06-16
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Progress in SMV back-end
Clifford Wolf
2015-06-15
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Progress in SMV back-end
Clifford Wolf
2015-06-15
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Added "write_smv" skeleton
Clifford Wolf
2015-06-15
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Removed debug code from write_smt2
Clifford Wolf
2015-06-14
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Added write_smt2 -mem
Clifford Wolf
2015-06-14
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Fixed cstr_buf for std::string with small string optimization
Clifford Wolf
2015-06-11
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Improvements in cellaigs.cc and "json -aig"
Clifford Wolf
2015-06-11
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AigMaker refactoring
Clifford Wolf
2015-06-10
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Added "json -aig"
Clifford Wolf
2015-06-10
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$mem cell in verilog backend : grouped writes by clock
luke whittlesey
2015-06-08
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Bug fix in $mem verilog backend + changed tests/bram flow of make test.
luke whittlesey
2015-06-04
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Improvements in BLIF front-end
Clifford Wolf
2015-05-24
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Some fixes for $mem in verilog back-end
Clifford Wolf
2015-05-20
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