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yosys
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Debian dgit repo for package yosys
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Author
Age
*
Merged OSX fixes from Siesh1oo with some modifications
Clifford Wolf
2014-03-13
*
Use log_abort() and log_assert() in BTOR backend
Clifford Wolf
2014-03-07
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Added $lut support to blif backend (by user eddiehung from reddit)
Clifford Wolf
2014-02-22
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Better handling of nameDef and nameRef in edif backend
Clifford Wolf
2014-02-21
*
Fixed instantiating multi-bit ports in edif backend
Clifford Wolf
2014-02-21
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Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param
Clifford Wolf
2014-02-21
*
modified btor synthesis script for correct use of splice command.
Ahmed Irfan
2014-02-12
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disabling splice command in the script
Ahmed Irfan
2014-02-11
*
register output corrected
Ahmed Irfan
2014-02-11
*
added concat and slice cell translation
Ahmed Irfan
2014-02-11
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
*
Fixed gcc compiler warnings with release build
Clifford Wolf
2014-02-06
*
Added BTOR backend README file
Clifford Wolf
2014-02-05
*
Added support for dump -append
Clifford Wolf
2014-02-04
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
*
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys
Clifford Wolf
2014-01-26
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*
root bug corrected
Ahmed Irfan
2014-01-25
*
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beautified write_intersynth
Johann Glaser
2014-01-25
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*
removed regex include
Ahmed Irfan
2014-01-24
*
merged clifford changes + removed regex
Ahmed Irfan
2014-01-24
*
Use techmap -share_map in btor scripts
Clifford Wolf
2014-01-24
*
Moved btor scripts to backends/btor/
Clifford Wolf
2014-01-24
*
slice bug corrected
Ahmed Irfan
2014-01-20
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assert feature
Ahmed Irfan
2014-01-20
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verilog default options pull
Ahmed Irfan
2014-01-17
*
slice error corrected
Ahmed Irfan
2014-01-16
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width issues
Ahmed Irfan
2014-01-15
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BTOR backend
Ahmed Irfan
2014-01-14
*
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Ahmed Irfan
2014-01-03
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*
Updated manual/command-reference-manual.tex
Clifford Wolf
2013-12-28
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*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
*
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btor
Ahmed Irfan
2014-01-03
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*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
*
Fixed gentb_constant handling in autotest backend
Clifford Wolf
2013-12-04
*
Added dump -m and -n options
Clifford Wolf
2013-11-29
*
Added proper dumping of signed/unsigned parameters to verilog backend
Clifford Wolf
2013-11-24
*
Added support for signed parameters in ilang
Clifford Wolf
2013-11-24
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Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
*
Added modelsim support to autotest
Clifford Wolf
2013-11-24
*
Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Implemented $_DFFSR_ expression generator in verilog backend
Clifford Wolf
2013-11-21
*
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
*
Silenced a gcc warning in spice backend
Clifford Wolf
2013-11-09
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Improved comments on topological sort in edif backend
Clifford Wolf
2013-11-04
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Added simple topological sort to edif backend
Clifford Wolf
2013-11-03
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Write yosys version to output files
Clifford Wolf
2013-11-03
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2013-11-03
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*
Ignore explicit unconnected ports in intersynth backend
Clifford Wolf
2013-11-03
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