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* Added init support to SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-18
* Progress in SMV back-endClifford Wolf2015-06-17
* Progress in SMV back-endClifford Wolf2015-06-17
* Progress in SMV back-endClifford Wolf2015-06-16
* Progress in SMV back-endClifford Wolf2015-06-15
* Progress in SMV back-endClifford Wolf2015-06-15
* Added "write_smv" skeletonClifford Wolf2015-06-15
* Removed debug code from write_smt2Clifford Wolf2015-06-14
* Added write_smt2 -memClifford Wolf2015-06-14
* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-11
* Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-11
* AigMaker refactoringClifford Wolf2015-06-10
* Added "json -aig"Clifford Wolf2015-06-10
* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-08
* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-04
* Improvements in BLIF front-endClifford Wolf2015-05-24
* Some fixes for $mem in verilog back-endClifford Wolf2015-05-20
* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-11
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| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-11
* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-10
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-10
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-08
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-07
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-09
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-08
* Added "port_directions" to write_json outputClifford Wolf2015-04-06
* Added "init" attribute support to verilog backendClifford Wolf2015-04-04
* Update READMEAhmed Irfan2015-04-03
* Delete btor.ysAhmed Irfan2015-04-03
* Update READMEAhmed Irfan2015-04-03
* separated memory next from write cellAhmed Irfan2015-04-03
* Added Verilog backend $dffsr supportClifford Wolf2015-03-18
* Documentation for JSON format, added attributesClifford Wolf2015-03-06
* Json bugfixClifford Wolf2015-03-03
* Json backend improvementsClifford Wolf2015-03-03
* Added write_blif -attrClifford Wolf2015-03-02
* Added JSON backendClifford Wolf2015-03-02
* Added $assume support to write_smt2Clifford Wolf2015-02-26
* Minor "write_smt2" help msg changeClifford Wolf2015-02-22
* Added "<mod>_a" and "<mod>_i" to write_smt2 outputClifford Wolf2015-02-22
* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-13
* Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-01
* Shorter "dump" optionsClifford Wolf2015-01-31
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-24
* Added dict/pool.sort()Clifford Wolf2015-01-24
* Cosmetic changes in verilog output formatClifford Wolf2015-01-02
* Fixed memory->start_offset handlingClifford Wolf2015-01-01
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