path: root/backends
Commit message (Expand)AuthorAge
* Merge branch 'btor' of Wolf2014-01-26
| * root bug correctedAhmed Irfan2014-01-25
* | beautified write_intersynthJohann Glaser2014-01-25
* removed regex includeAhmed Irfan2014-01-24
* merged clifford changes + removed regexAhmed Irfan2014-01-24
* Use techmap -share_map in btor scriptsClifford Wolf2014-01-24
* Moved btor scripts to backends/btor/Clifford Wolf2014-01-24
* slice bug correctedAhmed Irfan2014-01-20
* assert featureAhmed Irfan2014-01-20
* verilog default options pullAhmed Irfan2014-01-17
* slice error correctedAhmed Irfan2014-01-16
* width issuesAhmed Irfan2014-01-15
* BTOR backendAhmed Irfan2014-01-14
* Merge branch 'master' of into btorAhmed Irfan2014-01-03
| * Updated manual/command-reference-manual.texClifford Wolf2013-12-28
| * Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* | btorAhmed Irfan2014-01-03
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Fixed gentb_constant handling in autotest backendClifford Wolf2013-12-04
* Added dump -m and -n optionsClifford Wolf2013-11-29
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-24
* Added support for signed parameters in ilangClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Added modelsim support to autotestClifford Wolf2013-11-24
* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Silenced a gcc warning in spice backendClifford Wolf2013-11-09
* Improved comments on topological sort in edif backendClifford Wolf2013-11-04
* Added simple topological sort to edif backendClifford Wolf2013-11-03
* Write yosys version to output filesClifford Wolf2013-11-03
* Merge branch 'master' of Wolf2013-11-03
| * Ignore explicit unconnected ports in intersynth backendClifford Wolf2013-11-03
* | Added placeholder check to dfflibmap and cleaned up some other placeholder ch...Clifford Wolf2013-10-31
* Fixed hex string generation bug in edif backendClifford Wolf2013-10-27
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-17
* Improvements in EDIF backendClifford Wolf2013-09-17
* Added additional options to BLIF backendClifford Wolf2013-09-15
* Added BLIF backendClifford Wolf2013-09-15
* A couple of small fixes in SPICE backendClifford Wolf2013-09-15
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
* Added spice backendClifford Wolf2013-09-14
* Merge branch 'master' of Wolf2013-09-03