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Commit message (Expand)AuthorAge
* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-11
| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-11
* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-10
* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-10
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-08
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-07
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-09
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-08
* Added "port_directions" to write_json outputClifford Wolf2015-04-06
* Added "init" attribute support to verilog backendClifford Wolf2015-04-04
* Update READMEAhmed Irfan2015-04-03
* Delete btor.ysAhmed Irfan2015-04-03
* Update READMEAhmed Irfan2015-04-03
* separated memory next from write cellAhmed Irfan2015-04-03
* Added Verilog backend $dffsr supportClifford Wolf2015-03-18
* Documentation for JSON format, added attributesClifford Wolf2015-03-06
* Json bugfixClifford Wolf2015-03-03
* Json backend improvementsClifford Wolf2015-03-03
* Added write_blif -attrClifford Wolf2015-03-02
* Added JSON backendClifford Wolf2015-03-02
* Added $assume support to write_smt2Clifford Wolf2015-02-26
* Minor "write_smt2" help msg changeClifford Wolf2015-02-22
* Added "<mod>_a" and "<mod>_i" to write_smt2 outputClifford Wolf2015-02-22
* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-13
* Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-01
* Shorter "dump" optionsClifford Wolf2015-01-31
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-24
* Added dict/pool.sort()Clifford Wolf2015-01-24
* Cosmetic changes in verilog output formatClifford Wolf2015-01-02
* Fixed memory->start_offset handlingClifford Wolf2015-01-01
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-26
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Various fixes and improvements in "write_smt2 -bv"Clifford Wolf2014-12-25
* Various fixes and improvements in write_smt2Clifford Wolf2014-12-25
* Added support for most BV cell types to write_smt2Clifford Wolf2014-12-25
* Added "write_smt2 -bv" and other write_smt2 improvementsClifford Wolf2014-12-25
* Added write_smt2 (only gate level logic supported so far)Clifford Wolf2014-12-24
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
* Added $dffe support to write_verilogClifford Wolf2014-12-20
* Fixed another bug in write_blif handling of $lut cellsClifford Wolf2014-12-19
* Fixed writing of $lut cells in BLIF backendClifford Wolf2014-12-17
* Added "write_blif -undef" and support for special "-" true/false/undef typeClifford Wolf2014-12-14
* Added "write_blif -blackbox"Clifford Wolf2014-12-14
* Added "blif -unbuf" featureClifford Wolf2014-12-14
* Added log_warning() APIClifford Wolf2014-11-09
* Fixed generation of temp names in verilog backendClifford Wolf2014-11-07
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Merge branch 'master' of into btorAhmed Irfan2014-09-22
| * Sorting of object names in ilang backendClifford Wolf2014-09-19