yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Moved btor scripts to backends/btor/	Clifford Wolf	2014-01-24
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*	slice bug corrected	Ahmed Irfan	2014-01-20
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*	assert feature	Ahmed Irfan	2014-01-20
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*	verilog default options pull	Ahmed Irfan	2014-01-17
\| \| \| \|	shift operator width issues
*	slice error corrected	Ahmed Irfan	2014-01-16
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*	width issues	Ahmed Irfan	2014-01-15
\| \| \| \|	dff cell for more than one registers
*	BTOR backend	Ahmed Irfan	2014-01-14
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*	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	Ahmed Irfan	2014-01-03
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\| *	Updated manual/command-reference-manual.tex	Clifford Wolf	2013-12-28
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\| *	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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* \|	btor	Ahmed Irfan	2014-01-03
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
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*	Fixed gentb_constant handling in autotest backend	Clifford Wolf	2013-12-04
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*	Added dump -m and -n options	Clifford Wolf	2013-11-29
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*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24
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*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
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*	Added modelsim support to autotest	Clifford Wolf	2013-11-24
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
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*	Silenced a gcc warning in spice backend	Clifford Wolf	2013-11-09
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*	Improved comments on topological sort in edif backend	Clifford Wolf	2013-11-04
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*	Added simple topological sort to edif backend	Clifford Wolf	2013-11-03
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*	Write yosys version to output files	Clifford Wolf	2013-11-03
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-11-03
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\| *	Ignore explicit unconnected ports in intersynth backend	Clifford Wolf	2013-11-03
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* \|	Added placeholder check to dfflibmap and cleaned up some other placeholder ↵	Clifford Wolf	2013-10-31
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*	Fixed hex string generation bug in edif backend	Clifford Wolf	2013-10-27
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*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24
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*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24
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*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
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*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
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*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
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*	Added -buf, -true and -false options to blif backend	Clifford Wolf	2013-10-17
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*	Improvements in EDIF backend	Clifford Wolf	2013-09-17
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*	Added additional options to BLIF backend	Clifford Wolf	2013-09-15
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*	Added BLIF backend	Clifford Wolf	2013-09-15
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*	A couple of small fixes in SPICE backend	Clifford Wolf	2013-09-15
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*	Added spice testbench to techlibs/cmos	Clifford Wolf	2013-09-14
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*	Added spice backend	Clifford Wolf	2013-09-14
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-09-03
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\| *	Encode large (>32 bits) parameters as hex string in edif backend	Clifford Wolf	2013-08-28
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\| *	Improved edif backend	Clifford Wolf	2013-08-27
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* \|	Added -selected option to various backends	Clifford Wolf	2013-09-03
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*	More explicit integer output in verilog backend	Clifford Wolf	2013-08-22
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*	Added correct encoding of identifiers in EDIF backend	Clifford Wolf	2013-08-22
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*	Added edif backend (still under construction)	Clifford Wolf	2013-08-22
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