| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Avoid verilog-2k in verilog backend | Clifford Wolf | 2013-03-21 |
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| * | More support code for $sr cells | Clifford Wolf | 2013-03-14 |
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| * | Fixed a gcc compiler warning [-Wparentheses] | Clifford Wolf | 2013-03-03 |
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| * | Added more help messages | Clifford Wolf | 2013-03-01 |
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| * | initial import | Clifford Wolf | 2013-01-05 |
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index : yosys | |
| Debian dgit repo for package yosys |
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