yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
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\| *	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
\| *	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16
\| *	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16
\| *	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
\| *	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
\| *	Refactoring of CellType class	Clifford Wolf	2014-08-14
\| *	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02
\| *	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02
\| *	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
\| *	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
\| *	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
\| *	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
\| *	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29
\| *	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
\| *	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
\| *	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
\| *	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
\| *	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
\| *	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
\| *	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
\| *	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
\| *	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
\| *	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
\| *	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| *	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
\| *	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25
\| *	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
\| *	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
\| *	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
\| *	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
\| *	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
\| *	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
\| *	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
\| *	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
\| *	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21
\| *	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...	Clifford Wolf	2014-07-20
\| *	Added support for $bu0 to verilog backend	Clifford Wolf	2014-07-20
\| *	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13
\| *	Use log_abort() and log_assert() in BTOR backend	Clifford Wolf	2014-03-07
\| *	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22
\| *	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21
\| *	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21
\| *	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21
* \|	fixed memory next issue, when same memory is written in different case statement	ahmedirfan1983	2014-09-18
* \|	added $pmux cell translation	Ahmed Irfan	2014-09-02
\|/
*	modified btor synthesis script for correct use of splice command.	Ahmed Irfan	2014-02-12
*	disabling splice command in the script	Ahmed Irfan	2014-02-11
*	register output corrected	Ahmed Irfan	2014-02-11
*	added concat and slice cell translation	Ahmed Irfan	2014-02-11
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07